HYBRID NON-VOLATILE SOLID STATE MEMORY SYSTEM

• US 20080140918A1
• Filed: 12/07/2007
• Published: 06/12/2008
• Est. Priority Date: 12/11/2006
• Status: Abandoned Application

• Current Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Pantas
• Application Number:
  US11/952,648
• Publication Number:
  US 20080140918A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A solid state memory system comprises a first nonvolatile semiconductor (NVS) memory that has a first write cycle lifetime, a second nonvolatile semiconductor (NVS) memory that has a second write cycle lifetime that is different than the first write cycle lifetime, and a wear leveling module. The wear leveling module generates first and second wear levels for the first and second NVS memories based on the first and second write cycle lifetimes and maps logical addresses to physical addresses of one of the first and second NVS memories based on the first and second wear levels.

Claims

1. A solid state memory system comprising:

a first nonvolatile semiconductor (NVS) memory that has a first write cycle lifetime;

a second nonvolatile semiconductor (NVS) memory that has a second write cycle lifetime that is different than said first write cycle lifetime; and

a wear leveling module that generates first and second wear levels for said first and second NVS memories based on said first and second write cycle lifetimes and that maps logical addresses to physical addresses of one of said first and second NVS memories based on said first and second wear levels.

2. The solid state memory system of claim 1 wherein said first wear level is substantially based on a ratio of a first number of write operations performed on said first NVS memory to said first write cycle lifetime, and wherein said second wear level is substantially based on a ratio of a second number of write operations performed on said second NVS memory to said second write cycle lifetime.

3. The solid state memory system of claim 1 wherein said wear leveling module maps said logical addresses to said physical addresses of said second memory when said second wear level is less than said first wear level.

4. The solid state memory system of claim 1 wherein said first NVS memory has a first storage capacity that is greater than a second storage capacity of said second NVS memory.

5. The solid state memory system of claim 1 further comprising a mapping module that receives first and second frequencies for writing data to first and second of said logical addresses, wherein said wear leveling module biases mapping of said first of said logical addresses to said physical addresses of said second NVS memory when said first frequency is greater than said second frequency and said second wear level is less than said first wear level.

6. The solid state memory system of claim 5 wherein said wear leveling module biases mapping of said second of said logical addresses to said physical addresses of said first NVS memory.

7. The solid state memory system of claim 5 further comprising a write monitoring module that monitors subsequent frequencies of writing data to said first and second of said logical addresses and that updates said first and second frequencies based on said subsequent frequencies.

8. The solid state memory system of claim 1 further comprising a write monitoring module that measures first and second frequencies of writing data to first and second of said logical addresses, wherein said wear leveling module biases mapping of said first of said logical addresses to said physical addresses of said second NVS memory when said first frequency is greater than said second frequency and said second wear level is less than said first wear level.

9. The solid state memory system of claim 8 wherein said wear leveling module biases mapping of said second of said logical addresses to said physical addresses of said first NVS memory.

10. The solid state memory system of claim 1 further comprising a degradation testing module that:

writes data at a first predetermined time to one of said physical addresses;

generates a first stored data by reading data from said one of said physical addresses;

writes data to said one of said physical addresses at a second predetermined time;

generates a second stored data by reading data from said one of said physical addresses; and

generates a degradation value for said one of said physical addresses based on said first and second stored data.

11. The solid state memory system of claim 10 wherein said wear leveling module maps one of said logical addresses to said one of said physical addresses based on said degradation value.

12. The solid state memory system of claim 1 wherein:

said wear leveling module maps said logical addresses to said physical addresses of said first NVS memory when said second wear level is greater than or equal to a first predetermined threshold; and

said wear leveling module maps said logical addresses to said physical addresses of said second NVS memory when said first wear level is greater than or equal to a second predetermined threshold.

13. The solid state memory system of claim 1 wherein when write operations performed on a first block of said physical addresses of said first NVS memory during a predetermined period are greater than or equal to a predetermined threshold, said wear leveling module biases mapping of corresponding ones of said logical addresses from said first block to a second block of said physical addresses of said second NVS memory.

14. The solid state memory system of claim 1 wherein said wear leveling module identifies a first block of said physical addresses of said second NVS memory as a least used block (LUB).

15. The solid state memory system of claim 14 wherein said wear leveling module biases mapping of corresponding ones of said logical addresses from said first block to a second block of said physical addresses of said first NVS memory when available memory in said second NVS memory is less than or equal to a predetermined threshold.

16. The solid state memory system of claim 1 wherein said first NVS memory comprises a flash device and said second NVS memory comprises a phase-change memory device.

17. The solid state memory system of claim 16 wherein said first NVS memory comprises a Nitride Read-Only Memory (NROM) flash device.

18. The solid state memory system of claim 1 wherein said first write cycle lifetime is less than said second write cycle lifetime.

37. The solid state memory system of claim 1 wherein said second NVS memory includes single-level cell (SLC) flash memory and said first NVS memory include multi-level cell (MLC) flash memory.

38. The solid state memory system of claim 1 wherein said first NVS memory has a first access time and said second NVS memory has a second access time that is shorter than said first access time, wherein said wear leveling module maps first logical addresses to said first NVS memory and second logical addresses to said second NVS memory and wherein said first logical addresses are accessed less frequently than said second logical addresses.

19. A method comprising:

generating first and second wear levels for first and second nonvolatile semiconductor (NVS) memories based on first and second write cycle lifetimes, wherein said first and second write cycle lifetimes correspond to said first and second NVS memories, respectively; and

mapping logical addresses to physical addresses of one of said first and second NVS memories based on said first and second wear levels.

20. The method of claim 19 wherein said first wear level is substantially based on a ratio of a first number of write operations performed on said first NVS memory to said first write cycle lifetime, and wherein said second wear level is substantially based on a ratio of a second number of write operations performed on said second NVS memory to said second write cycle lifetime.

21. The method of claim 19 further comprising mapping said logical addresses to said physical addresses of said second memory when said second wear level is less than said first wear level.

22. The method of claim 19 wherein said first NVS memory has a first storage capacity that is greater than a second storage capacity of said second NVS memory.

23. The method of claim 19 wherein said first write cycle lifetime is less than said second write cycle lifetime.

24. The method of claim 19 further comprising:

receiving first and second frequencies for writing data to first and second of said logical addresses; and

biasing mapping of said first of said logical addresses to said physical addresses of said second NVS memory when said first frequency is greater than said second frequency and said second wear level is less than said first wear level.

25. The method of claim 24 further comprising biasing mapping of said second of said logical addresses to said physical addresses of said first NVS memory.

26. The method of claim 24 further comprising:

monitoring subsequent frequencies of writing data to said first and second of said logical addresses; and

updating said first and second frequencies based on said subsequent frequencies.

27. The method of claim 19 further comprising:

measuring first and second frequencies of writing data to first and second of said logical addresses; and

biasing mapping of said first of said logical addresses to said physical addresses of said second NVS memory when said first frequency is greater than said second frequency and said second wear level is less than said first wear level.

28. The method of claim 27 further comprising biasing mapping of said second of said logical addresses to said physical addresses of said first NVS memory.

29. The method of claim 19 further comprising:

writing data at a first predetermined time to one of said physical addresses;

generating a first stored data by reading data from said one of said physical addresses;

writing data to said one of said physical addresses at a second predetermined time;

generating a second stored data by reading data from said one of said physical addresses; and

generating a degradation value for said one of said physical addresses based on said first and second stored data.

30. The method of claim 29 further comprising mapping one of said logical addresses to said one of said physical addresses based on said degradation value.

31. The method of claim 19 further comprising:

mapping said logical addresses to said physical addresses of said first NVS memory when said second wear level is greater than or equal to a first predetermined threshold; and

mapping said logical addresses to said physical addresses of said second NVS memory when said first wear level is greater than or equal to a second predetermined threshold.

32. The method of claim 19 wherein when write operations performed on a first block of said physical addresses of said first NVS memory during a predetermined period are greater than or equal to a predetermined threshold, biasing mapping of corresponding ones of said logical addresses from said first block to a second block of said physical addresses of said second NVS memory.

33. The method of claim 19 further comprising identifying a first block of said physical addresses of said second NVS memory as a least used block (LUB).

34. The method of claim 33 further comprising biasing mapping of corresponding ones of said logical addresses from said first block to a second block of said physical addresses of said first NVS memory when available memory in said second NVS memory is less than or equal to a predetermined threshold.

35. The method of claim 19 wherein said first NVS memory comprises a flash device and said second NVS memory comprises a phase-change memory device.

36. The method of claim 35 wherein said first NVS memory comprises a Nitride Read-Only Memory (NROM) flash device.

39. The method of claim 19 wherein said second NVS memory includes single-level cell (SLC) flash memory and said first NVS memory include multi-level cell (MLC) flash memory.

40. The method of claim 19 wherein said first NVS memory has a first access time and said second NVS memory has a second access time that is shorter than said first access time, the method further comprising mapping first logical addresses to said first NVS memory and second logical addresses to said second NVS memory, wherein said first logical addresses are accessed less frequently than said second logical addresses.