Reconfigurable memory module and method

• US 20080140952A1
• Filed: 02/08/2008
• Published: 06/12/2008
• Est. Priority Date: 06/19/2003
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M., Lee, Terry R.
• Granted Patent: US 7,818,712 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4239 with asynchronous protocol

Abstract

A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

Claims

1. A memory system, comprising:

a plurality of memory devices arranged in a plurality of ranks; and

a memory interface device coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module in a plurality of different data formats, the memory hub being operable to simultaneously address and couple data to and/or from different numbers of ranks of the memory devices in each of the different data formats.

62. The memory system of claim 1, further comprising a programmable storage device coupled to the memory interface device, the programmable storage device being programmed to control the operating mode of the memory interface device.

63. The memory system of claim 1 wherein the memory devices in each rank are collectively operable to read or write N-bit data words, and wherein the memory interface device further comprises an input/output port that is operable to receive or transmit M*N-bit data words, where M is the number of ranks of memory devices in the memory system.

64. The memory system of claim 1 wherein the memory devices in each rank are collectively operable to read or write N-bit data words in a first period of time, and wherein the memory interface device further comprises an input/output port that is operable to receive or transmit M*N data bits in the first period of time, where M is the number of ranks of memory devices in the memory system.

65. The memory system of claim 1 wherein the plurality of memory devices and the memory interface device are mounted in a common memory module.

66. The memory system of claim 65 wherein the memory interface device comprises a memory hub mounted in the memory module.

2-61. -61. (canceled)

67. A memory system, comprising:

a plurality of memory devices arranged in a plurality of ranks; and

a memory hub coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module in a plurality of different modes, the memory hub being operable to simultaneously couple data to and/or from different numbers of ranks of the memory devices in each of the different data modes.

68. The memory system of claim 67 wherein the memory devices in each rank are collectively operable to read or write N-bit data words, and wherein the memory interface device further comprises an input/output port that is operable to receive or transmit M*N-bit data words, where M is the number of ranks of memory devices in the memory system.

69. The memory system of claim 67 wherein the memory devices in each rank are collectively operable to read or write N-bit data words in a first period of time, and wherein the memory interface device further comprises an input/output port that is operable to receive or transmit M*N data bits in the first period of time, where M is the number of ranks of memory devices in the memory system.

70. The memory system of claim 67 wherein the plurality of memory devices and the memory interface device are mounted in a common memory module.

71. The memory system of claim 70 wherein the memory interface device comprises a memory hub mounted in the memory module.

72. A processor-based electronic system, comprising:

a processor operable to execute a plurality of different application programs;

a controller coupled to the processor, the controller being operable to receive a memory request from the processor and to transmit a corresponding memory request from the controller;

an input device coupled to the processor;

an output device coupled to the processor; and

a plurality of memory modules coupled to the processor, each of the memory modules comprising;

a plurality of memory devices arranged in a plurality of ranks; and

a memory hub coupled to the memory devices in each of the ranks and being operable to receive memory requests, the memory hub being programmable to configure the memory module in a plurality of data formats depending upon the application program being executed by the processor, each of the data formats corresponding to a respective number of ranks of memory devices that are simultaneously accessed.

73. The electronic system of claim 72 wherein the memory devices in each rank are collectively operable to read or write N-bit data words, and wherein the memory hub is operable to receive or transmit M*N-bit data words, where M is the number of ranks of memory devices in the memory module.

74. The electronic system of claim 72 wherein the memory devices in each rank are collectively operable to read or write N-bit data words in a first period of time, and wherein the memory hub is operable to receive or transmit M*N data bits in the first period of time, where M is the number of ranks of memory devices in the memory module.

75. The electronic system of claim 72 wherein the memory hubs in at least two of the memory modules are programmed to configure the memory module in different data formats at the same time.

76. A processor-based electronic system, comprising:

a processor operable to execute a plurality of different application programs;

a controller coupled to the processor, the controller being operable to receive a memory request from the processor and to transmit a corresponding memory request from the controller;

an input device coupled to the processor;

an output device coupled to the processor; and

a plurality of memory modules coupled to the processor, each of the memory modules comprising;

a plurality of memory devices arranged in a plurality of ranks; and

a memory hub coupled to the memory devices in each of the ranks and being operable to receive memory requests, the memory hub being programmable to configure the memory module in a plurality of modes depending upon the application program being executed by the processor, each of the modes corresponding to a respective number of ranks of memory devices that are simultaneously accessed.

77. The electronic system of claim 76 wherein the memory devices in each rank are collectively operable to read or write N-bit data words, and wherein the memory hub is operable to receive or transmit M*N-bit data words, where M is the number of ranks of memory devices in the memory module.

78. The electronic system of claim 76 wherein the memory devices in each rank are collectively operable to read or write N-bit data words in a first period of time, and wherein the memory hub is operable to receive or transmit M*N data bits in the first period of time, where M is the number of ranks of memory devices in the memory module.

79. The electronic system of claim 76 wherein the memory hubs in at least two of the memory modules are programmed to configure the memory module in different data formats at the same time.

80. A processor-based electronic system, comprising:

a processor;

a controller coupled to the processor, the controller being operable to receive a memory request from the processor and to transmit a corresponding memory request from the controller;

an input device coupled to the processor;

an output device coupled to the processor;

a memory access device other than the processor; and

a plurality of memory modules coupled to the processor and to the at least one memory access device other than the processor, each of the memory modules comprising;

a plurality of memory devices arranged in a plurality of ranks; and

a memory hub coupled to the memory devices in each of the ranks and being operable to receive memory requests, the memory hub being programmable to configure the memory module in a plurality of different data formats depending upon whether the memory module is being accessed by the processor or the memory access device other than the processor, each of the different data formats corresponding to a respective number of ranks of memory devices that are simultaneously accessed.

81. The electronic system of claim 80 wherein the memory devices in each rank are collectively operable to read or write N-bit data words, and wherein the memory hub is operable to receive or transmit M*N-bit data words, where M is the number of ranks of memory devices in the memory module.

82. The electronic system of claim 80 wherein the memory devices in each rank are collectively operable to read or write N-bit data words in a first period of time, and wherein the memory hub is operable to receive or transmit M*N data bits in the first period of time, where M is the number of ranks of memory devices in the memory module.

83. The electronic system of claim 80 wherein the memory hubs in at least two of the memory modules are programmed to configure the memory module in different data formats at the same time.

84. The electronic system of claim 80 wherein a first of the plurality of memory hubs is accessed by the processor and is configured in a first data format, and a second of the plurality of memory hubs is accessed by the device other than the processor and is configured in a second data format data is different from the first data format.

85. A processor-based electronic system, comprising:

a processor;

a controller coupled to the processor, the controller being operable to receive a memory request from the processor and to transmit a corresponding memory request from the controller;

an input device coupled to the processor;

an output device coupled to the processor;

a memory access device other than the processor; and

a plurality of memory modules coupled to the processor and to the at least one memory access device other than the processor, each of the memory modules comprising;

a plurality of memory devices arranged in a plurality of ranks; and

a memory hub coupled to the memory devices in each of the ranks and being operable to receive memory requests, the memory hub being programmable to configure the memory module in a plurality of modes depending upon whether the memory module is being accessed by the processor or the memory access device other than the processor, each of the modes corresponding to a respective number of ranks of memory devices that are simultaneously accessed.

86. The electronic system of claim 85 wherein the memory devices in each rank are collectively operable to read or write N-bit data words, and wherein the memory hub is operable to receive or transmit M*N-bit data words, where M is the number of ranks of memory devices in the memory module.

87. The electronic system of claim 85 wherein the memory devices in each rank are collectively operable to read or write N-bit data words in a first period of time, and wherein the memory hub is operable to receive or transmit M*N data bits in the first period of time, where M is the number of ranks of memory devices in the memory module.

88. The electronic system of claim 85 wherein the memory hubs in at least two of the memory modules are programmed to configure the memory module in different data formats at the same time.

89. The electronic system of claim 85 wherein a first of the plurality of memory hubs is accessed by the processor and is configured in a first mode, and a second of the plurality of memory hubs is accessed by the device other than the processor and is configured in a second mode that is different from the first mode.

90. A method of accessing data in a plurality of memory devices, the method comprising:

dividing the memory devices into a plurality of ranks; and

selectively accessing the memory devices in one of a plurality of different modes, each of the different modes causing different numbers of ranks of memory devices to be simultaneously accessed.

91. The method of claim 90 wherein the act of selectively accessing the memory devices in one of a plurality of different modes comprises:

determining which of a plurality of memory access devices is attempting to access the memory devices; and

selecting the mode based on the determination of which of the plurality of memory access devices is attempting to access the memory devices.

92. The method of claim 90 wherein the memory devices are part of a processor-based electronic system in which a processor can execute a plurality of different applications, and wherein the act of selectively accessing the memory devices in one of a plurality of different modes comprises:

determining which of the plurality of applications is being executed in the processor-based electronic system; and

selecting the mode based on the determination of which of the plurality of applications is being executed.

93. The method of claim 90 wherein each of the different modes results in data being transferred to or from the memory devices in a different respective data format.

94. A method of accessing data in a plurality of memory devices, the method comprising:

dividing the memory devices into a plurality of groups of memory devices;

dividing the memory devices in each group into a plurality of ranks;

accessing one of the groups of the memory devices by simultaneously accessing a first number of ranks of memory devices in the group; and

accessing another of the groups of the memory devices by simultaneously accessing a second number of ranks of memory devices in the group, the second number being different from the first number.

95. The method of claim 94 wherein the act of accessing the memory devices comprises:

determining which of a plurality of memory access devices is attempting to access the memory devices; and

selecting the group of memory devices based on the determination of which of the plurality of memory access devices is attempting to access the memory devices.

96. The method of claim 94 wherein the memory devices are part of a processor-based electronic system in which a processor can execute a plurality of different applications, and wherein the act of selectively accessing the memory devices comprises:

determining which of the plurality of applications is being executed in the processor-based electronic system; and

selecting the group of memory devices based on the determination of which which of the plurality of applications is being executed.

97. The method of claim 94 wherein are being transferred to or from the memory devices in each of the groups in different respective data formats.

98. The method of claim 94 wherein the memory devices in each of the groups are mounted on different respective memory modules.