INTEGRATED MECHANISM FOR SUSPENSION AND DEALLOCATION OF COMPUTATIONAL THREADS OF EXECUTION IN A PROCESSOR

• US 20080140998A1
• Filed: 12/03/2007
• Published: 06/12/2008
• Est. Priority Date: 08/28/2003
• Status: Active Grant

• Current Assignee: MIPS Tech, LLC
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Kissell, Kevin D.
• Granted Patent: US 7,676,660 B2
• Time in Patent Office: Days
• US Class Current: 712/214
• CPC Class Codes: G06F 8/4442 Reducing the number of cache misses; Data prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/54 Interprogram communication

Abstract

A microprocessor core includes a plurality of inputs that indicate whether a corresponding plurality of independently occurring events has occurred. The inputs are non-memory address inputs. The core also includes a yield instruction in its instruction set architecture, comprising a user-visible output operand and an explicit input operand. The input operand specifies one or more of the independently occurring events. The yield instruction instructs the microprocessor core to suspend issuing for execution instructions of a program thread until at least one of the independently occurring events specified by the input operand has occurred. The program thread contains the yield instruction. The yield instruction further instructs the microprocessor core to return a value in the output operand indicating which of the independently occurring events occurred to cause the microprocessor core to resume issuing the instructions of the program thread.

Claims

1. A microprocessor core, comprising:

a plurality of inputs, configured to indicate whether a corresponding plurality of independently occurring events has occurred, wherein said plurality of inputs are non-memory address inputs; and

a yield instruction, included in the instruction set of the architecture of the microprocessor core, comprising a user-visible output operand and an explicit input operand, said input operand for specifying one or more of said plurality of independently occurring events;

wherein said yield instruction instructs the microprocessor core to suspend issuing for execution instructions of a program thread until at least one of said independently occurring events specified by said input operand has occurred, wherein said program thread contains said yield instruction;

wherein said yield instruction further instructs the microprocessor core to return a value in said output operand indicating which of said independently occurring events occurred to cause the microprocessor core to resume issuing said instructions of said program thread.

2. The microprocessor core of claim 1, wherein said yield instruction further instructs the microprocessor core to resume issuing an instruction of said thread immediately following said yield instruction, rather than executing an event handling routine to handle said at least one occurred event.

3. The microprocessor core of claim 1, wherein when said explicit input operand is a predetermined value, said yield instruction instructs the microprocessor core to terminate said thread, rather than to suspend issuing instructions of said thread.

4. The microprocessor core of claim 1, wherein when said explicit input operand is a predetermined value, said yield instruction instructs the microprocessor core to unconditionally resume issuing instructions of said thread, rather than to suspend issuing instructions of said thread.

5. The microprocessor core of claim 1, wherein at least one of said plurality of events is generated by an input/output device.

6. The microprocessor core of claim 1, wherein at least one of said plurality of inputs is configured to receive an interrupt request signal.

7. The microprocessor core of claim 1, wherein at least one of said plurality of inputs is configured to receive a signal indicating a cache miss.

8. The microprocessor core of claim 1, further comprising:

a mask register, programmable by system software for storing a value specifying one or more of said plurality of inputs, wherein the microprocessor core raises an exception to the yield instruction when said value specifies one or more of said plurality of inputs unspecified by said mask register value.

9. The microprocessor core of claim 8, wherein said yield instruction further instructs the microprocessor core to return said value qualified by said mask register value.

10. The microprocessor core of claim 8, further comprising:

a plurality of thread contexts, configured to store a state of a plurality of program threads concurrently executed by the microprocessor core, each of said plurality of thread contexts comprising a program counter and a general purpose register set;

wherein said mask register is global to said plurality of thread contexts.

11. The microprocessor core of claim 1, further comprising:

a plurality of thread contexts, configured to store a state of a plurality of program threads concurrently executed by the microprocessor core, each of said plurality of thread contexts comprising a program counter and a general purpose register set;

wherein said plurality of inputs are non-specific to said plurality of thread contexts, thereby facilitating migration of said plurality of program threads among said plurality of thread contexts by an operating system.

12. The microprocessor core of claim 1, wherein said explicit input operand specifies a Boolean function performed by the microprocessor core on said plurality of inputs, wherein said yield instruction instructs the microprocessor core to suspend issuing for execution instructions of said program thread until an output of said Boolean function indicates at least one of said independently occurring events specified by said input operand has occurred.

13. The microprocessor core of claim 1, wherein said plurality of inputs are mapped from a plurality of signal sources according to a plurality of programmable registers coupled to said plurality of inputs.

14. A method for conditionally suspending issuing instructions of a program thread in a microprocessor core having an instruction set of its architecture, the method comprising:

receiving a plurality of inputs configured to indicate whether a corresponding plurality of independently occurring events has occurred, wherein said plurality of inputs are non-memory address inputs;

issuing a yield instruction, said instruction included in the instruction set of the architecture of the microprocessor core, said instruction comprising a user-visible output operand and an explicit input operand, said input operand for specifying one or more of said plurality of independently occurring events;

suspending issuing for execution instructions of a program thread until at least one of said independently occurring events specified by said input operand has occurred, wherein said program thread contains said yield instruction; and

returning a value in said output operand indicating which of said independently occurring events occurred to cause the microprocessor core to resume issuing said instructions of said program thread.

15. The method of claim 14, wherein said resuming comprises:

resuming issuing an instruction of said thread immediately following said yield instruction, rather than executing an event handling routine to handle said at least one occurred event.

16. The method of claim 14, further comprising:

unconditionally resuming issuing instructions of said thread, rather than said suspending issuing instructions of said thread, when said explicit input operand is a predetermined value.

17. The method of claim 14, further comprising:

terminating said thread, rather than said suspending issuing instructions of said thread, when said explicit input operand is a predetermined value.

18. The method of claim 14, wherein at least one of said plurality of inputs is configured to receive an interrupt request signal.

19. The method of claim 14, wherein at least one of said plurality of inputs is configured to receive a signal indicating a cache miss.

20. The method of claim 14, further comprising:

programming a mask register of the microprocessor to store a value specifying one or more of said plurality of inputs, wherein said programming is performed by system software executing on the microprocessor;

raising an exception to the yield instruction when said value specifies one or more of said plurality of inputs unspecified by said mask register value.

21. A computer program product for use with a computing device, the computer program product comprising:

a computer usable medium, having computer readable program code embodied in said medium, for providing a microprocessor core, said computer readable program code comprising;

first program code for providing a plurality of inputs, configured to indicate whether a corresponding plurality of independently occurring events has occurred, wherein said plurality of inputs are non-memory address inputs; and

second program code for providing a yield instruction, included in the instruction set of the architecture of the microprocessor core, comprising a user-visible output operand and an explicit input operand, said input operand for specifying one or more of said plurality of independently occurring events;

wherein said yield instruction instructs the microprocessor core to suspend issuing for execution instructions of a program thread until at least one of said independently occurring events specified by said input operand has occurred, wherein said program thread contains said yield instruction;

wherein said yield instruction further instructs the microprocessor core to return a value in said output operand indicating which of said independently occurring events occurred to cause the microprocessor core to resume issuing said instructions of said program thread.

22. The computer program product of claim 21, wherein said yield instruction further instructs the microprocessor core to resume issuing an instruction of said thread immediately following said yield instruction, rather than executing an event handling routine to handle said at least one occurred event.

23. The computer program product of claim 21, wherein when said explicit input operand is a predetermined value, said yield instruction instructs the microprocessor core to unconditionally resume issuing instructions of said thread, rather than to suspend issuing instructions of said thread.

24. The computer program product of claim 21, wherein when said explicit input operand is a predetermined value, said yield instruction instructs the microprocessor core to terminate said thread, rather than to suspend issuing instructions of said thread.

25. The computer program product of claim 21, further comprising:

third program code for providing a plurality of thread contexts, configured to store a state of a plurality of program threads concurrently executed by the microprocessor core, each of said plurality of thread contexts comprising a program counter and a general purpose register set;

wherein said plurality of inputs are non-specific to said plurality of thread contexts, thereby facilitating migration of said plurality of program threads among said plurality of thread contexts by an operating system.