APPARATUS, SYSTEM, AND METHOD FOR MANAGING DATA USING A DATA PIPELINE

• US 20080141043A1
• Filed: 12/06/2007
• Published: 06/12/2008
• Est. Priority Date: 12/06/2006
• Status: Active Grant

• Current Assignee: Unification Technologies LLC (Acacia Research Corporation)
• Original Assignee: Fusion-IO Incorporated (Western Digital Corporation)
• Inventors: Flynn, David, Thatcher, Jonathan, Zappe, Michael, Lagerstedt, Bert, Strasser, John
• Granted Patent: US 8,266,496 B2
• Time in Patent Office: Days
• US Class Current: 713/193
• CPC Class Codes: G06F 1/183 Internal mounting support structures, e.g. for printed circuit boards, internal connecting means for buses G06F13/409
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
• CPC Class Codes: G06F 2211/002 Bus
• CPC Class Codes: G06F 2211/103 Hybrid, i.e. RAID systems with parity comprising a mix of RAID types
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/70 Details relating to dynamic memory management
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7208 : Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0604 : Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0608 : Saving storage space on storage systems
• CPC Class Codes: G06F 3/0613 : in relation to throughput
• CPC Class Codes: G06F 3/0619 : in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0643 : Management of files
• CPC Class Codes: G06F 3/065 : Replication mechanisms
• CPC Class Codes: G06F 3/0652 : Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0656 : Data buffering arrangements
• CPC Class Codes: G06F 3/0659 : Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 : Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0685 : Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 9/52 : Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/54 : Interprogram communication
• CPC Class Codes: H04L 67/02 : based on web technology, e.g. hypertext transfer protocol [HTTP]
• CPC Class Codes: H04L 67/1097 : for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H05K 7/1444 : Complex or three-dimensional-arrangements; Stepped or dual mother boards
• CPC Class Codes: H05K 7/1487 : Blade assemblies, e.g. blade cases or inner arrangements within a blade
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus, system, and method are disclosed for managing data in a solid-state storage device. A solid-state storage and solid-state controller are included. The solid-state storage controller includes a write data pipeline and a read data pipeline The write data pipeline includes a packetizer and an ECC generator. The packetizer receives a data segment and creates one or more data packets sized for the solid-state storage. The ECC generator generates one or more error-correcting codes (“ECC”) for the data packets received from the packetizer. The read data pipeline includes an ECC correction module, a depacketizer, and an alignment module. The ECC correction module reads a data packet from solid-state storage, determines if a data error exists using corresponding ECC and corrects errors. The depacketizer checks and removes one or more packet headers. The alignment module removes unwanted data, and re-formats the data as data segments of an object.

Claims

1. An apparatus to manage data in a solid-state storage device, the apparatus comprising:

a solid-state storage, the solid-state storage comprising an array of non-volatile, solid-state data storage elements accessed using a bi-directional storage input/output (“

I/O”

) bus; and

a solid-state storage controller in communication with the solid-state storage via the storage I/O bus, the solid-state controller comprising a write data pipeline to write data segments to the solid-state storage, the data segment comprising at least a portion of an object, the write data pipeline comprising

a packetizer that receives a data segment to be written to the solid-sate storage and creates one or more data packets sized for the solid-state storage, each data packet comprising a header and data from the data segment; and

an ECC generator that generates one or more error-correcting codes (“

ECC”

) for the one or more data packets received from the packetizer prior to writing the data packets to the solid-state storage; and

 

a read data pipeline to requested data packets stored in the solid-state storage device in response to on a read request, the read data pipeline comprising

an ECC correction module that receives a requested data packet from the solid-state storage, determines if a data error exists in a requested data packet using ECC stored with the requested data packet, corrects an error in the requested data packet in response to determining that the error exists and the error being correctable by the ECC, and interrupts in response to determining that the detected data error is uncorrectable;

a depacketizer that receives a requested data packet from the ECC correction module and checks and removes one or more packet headers; and

an alignment module that receives data from the depacketizer, removes unwanted data, and re-formats the data as data segments of an object in a form compatible with a device requesting the data segment prior to transmission to the requesting device.

2. The apparatus of claim 1, wherein

the write data pipeline further comprises an input buffer that receives and stores the data segment to be written to the solid-state storage prior to the packetizer receiving the data segment;

and

the read data pipeline further comprises an output buffer that receives requested data packets from the alignment module and stores the data packets prior to transmission to the requesting device.

3. The apparatus of claim 2, wherein

the write data pipeline further comprises an encryption module that encrypts a data segment received from the input buffer prior sending the data segment to the packetizer, the data segment encrypted using an encryption key received in conjunction with the data segment;

and

the read data pipeline further comprises a decryption module that decrypts a data segment formatted by the depacketizer prior to sending the data segment to the output buffer, the data segment decrypted using an encryption key received in conjunction with the read request.

4. The apparatus of claim 3, wherein the encryption module encrypts a first data segment with a first received encryption key and encrypts a second data segment with a second received encryption key.

5. The apparatus of claim 1, wherein

the write data pipeline further comprises a write synchronization buffer that buffers data packets received from the ECC generator prior to writing the data packets to the solid-state storage, the write synch buffer at a boundary between a local clock domain and a solid-state storage clock domain;

and

the read data pipeline further comprises a read synchronization buffer that buffers one or more requested data packets read from the solid-state storage prior to processing by the read data pipeline, the read synchronization buffer at a boundary between the solid-state storage clock domain and the local bus clock domain.

6. The apparatus of claim 1, wherein the packetizer receives data segments from one of a device writing the data segment to the solid-state storage and from the read data pipeline, wherein a data segment received from the read data pipeline comprises data being copied from an erase block within the solid-state storage prior to erasing data in the erase block.

7. The apparatus of claim 1, wherein

the write data pipeline further comprises a compression module that compresses the data segment prior to sending the data segment to the packetizer;

and

the read data pipeline further comprising a decompression module that decompresses a data segment formatted by the depacketizer.

8. The apparatus of claim 7, wherein the compression module compresses a first data segment with a first compression routine and either passes along a second data segment without compression or compresses the second data segment with a second compression routine.

9. The apparatus of claim 1, wherein

the write data pipeline further comprises a media encryption module that receives the one or more data packets from the packetizer and encrypts the one or more data packets using an encryption key unique to the solid-state storage device prior to sending the data packets to the ECC generator;

and

the read data pipeline further comprises a media decryption module that receives one or more encrypted requested data packets from the ECC correction module and decrypts the one or more requested data packets using the encryption key unique to the solid-state storage device prior to sending the one or more requested data packets to the depacketizer.

10. The apparatus device of claim 9, wherein the media encryption module encrypts a first data packet with the encryption key unique to the solid-state storage device and passes on a second data packet to the ECC generator without encryption.

11. The apparatus of claim 1, wherein the solid-state storage device further comprises a system I/O bus connecting the controller to an external device.

12. The apparatus of claim 11, wherein the solid-state storage device is configured in a dual-inline memory module (“

DIMM”

).

13. The apparatus of claim 1, wherein the data packets written to the solid-state storage by the write data pipeline and the requested data packets read from the solid-state memory into the read data pipeline are multiplexed together onto the storage I/O bus.

14. The apparatus of claim 1, wherein the solid-state storage of the solid-state storage device comprises flash memory.

15. The apparatus of claim 1, wherein the write data pipeline further comprises a write program module comprising one or more user-definable functions within the write data pipeline.

16. The apparatus of claim 1, wherein the read data pipeline further comprises a read program module comprising one or more user-definable functions within the read data pipeline.

17. A solid-state storage device comprising:

a solid-state storage arranged in two or more banks, each bank separately accessible and each bank comprising two or more solid-state storage elements accessed in parallel by a storage input/output (“

I/O”

) bus, the solid-state storage comprising solid-state, non-volatile memory; and

a bank interleave controller that

directs one or more commands to one or more queues, each bank comprising a queue in the bank interleave controller; and

coordinates among the banks execution of the commands stored in the queues, wherein a command of a first type executes on one bank while a command of a second type executes on a second bank.

18. A system to manage data in a solid-state storage device, the system comprising:

a computer;

a system bus; and

a solid-state storage device coupled to the computer through the system bus, the solid-state storage device comprising a solid-state storage comprising an array of non-volatile, solid-state data storage elements accessed using a bi-directional storage input/output (“

I/O”

) bus and a solid-state storage controller in communication with the solid-state storage via the storage I/O bus, the solid-state controller comprising a write data pipeline to write data segments to the solid-state storage, the data segment comprising at least a portion of an object, the write data pipeline comprising

a packetizer that receives a data segment to be written to the solid-sate storage and creates one or more data packets sized for the solid-state storage, each data packet comprising a header and data from the data segment; and

an ECC generator that generates error-correcting code (“

ECC”

) for the one or more data packets received from the packetizer prior to writing the data packets to the solid-state storage; and

 

a read data pipeline to request data packets stored in the solid-state storage device in response to a read request, the read data pipeline comprising

an ECC correction module that receives a requested data packet from the solid-state storage, determines if a data error exists in a requested data packet using ECC stored with the requested data packet, corrects an error in the requested data packet in response to determining that the error exists and the error being correctable by the ECC, and interrupts in response to determining that the detected data error is uncorrectable;

a depacketizer that receives a requested data packet from the ECC correction module and checks and removes one or more packet headers; and

an alignment module that receives data from the depacketizer, removes unwanted data, and re-formats the data as data segments of an object in a form compatible with a device requesting the data segment prior to transmission to the requesting device.

19. The system of claim 18, wherein

the write data pipeline further comprises

an input buffer that receives and stores the data segment to be written to the solid-state storage prior to the packetizer receiving the data segment;

and

an encryption module that encrypts a data segment received from the input buffer prior sending the data segment to the packetizer, the data segment encrypted using an encryption key received in conjunction with the data segment; and

the read data pipeline further comprises

an output buffer that receives requested data packets from the alignment module and stores the data packets prior to transmission to the requesting device; and

a decryption module that decrypts a data segment formatted by the depacketizer prior to sending the data segment to the output buffer, the data segment decrypted using an encryption key received in conjunction with the read request.

20. The system of claim 18, further comprising a client in communication with the computer over a computer network, the client transmitting data requests to the solid-state storage device coupled to the computer over the computer network.

21. The system of claim 18, wherein the system bus comprises one of a peripheral component interconnect express (“

PCI-e”

) bus, a Serial Advanced Technology Attachment (“

serial ATA”

) bus, an Ethernet bus, a universal serial bus (“

USB”

) connection, and an Institute of Electrical and Electronics Engineers (“

IEEE”

) 1394 bus.

22. The system of claim 18, wherein the computer accesses data in the solid-state storage device using direct memory access (“

DMA”

).

23. A computer program product comprising a computer readable medium having computer usable program code executable to perform operations for managing data in a solid-state storage device, the operations of the computer program product comprising:

receiving in an input buffer a data segment to be written to a solid-state storage of a solid-state storage device, the data segment comprising at least a portion of an object, the solid-state storage comprising an array of non-volatile, solid-state data storage elements;

receiving the data segment from the input buffer and packetizing the data segments, packetizing the data segments comprising creating one or more data packets sized for the solid-state storage, each data packet comprising a header and data from the data segment;

receiving the data packets after packetizing and generating error-correcting code (“

ECC”

) for the data packets;

buffering within a write synchronization buffer the data packets and corresponding ECC prior to writing the data packets and ECC to the solid-state storage, the write synch buffer at a boundary between a local clock domain and a solid-state storage clock domain; and

writing the data packets from the write synchronization buffer to the solid-state storage over a bi-directional storage input/output (“

I/O”

) bus.

24. The computer program product of claim 23, wherein further comprising:

buffering, in a read synchronization buffer, one or more requested data packets read from the solid-state storage, received over the storage I/O bus, prior to processing the requested data packets in response to a read request, the read synchronization buffer at a boundary between a solid-state storage clock domain and a local bus clock domain;

receiving the requested data packets held in the read synchronization buffer and correcting errors within the requested data packets, correcting errors comprising determining if a data error exists in a requested data packet using ECC stored with the requested data packet, correcting an error in the requested data packet in response to determining that the error exists and the error being correctable by the ECC, and interrupting in response to determining that the detected data error is uncorrectable;

receiving requested data packets after correcting errors and depacketizing the data packets, depacketizing the data packets comprising checking and removing one or more packet headers;

receiving data packets after depacketizing, removing unwanted data, and re-formatting the data packets as data segments of an object in a form compatible with a device requesting the data segment; and

receiving, in an output buffer, requested data packets after depacketizing and storing the data packets prior to transmission to the requesting device.