Systems and Methods for Reducing di/dt Using Clock Signals Having Variable Delays

• US 20080141062A1
• Filed: 12/12/2006
• Published: 06/12/2008
• Est. Priority Date: 12/12/2006
• Status: Active Grant

• Current Assignee: Hiroaki Yamaoka
• Original Assignee: Hiroaki Yamaoka
• Inventors: Yamaoka, Hiroaki
• Granted Patent: US 7,685,458 B2
• Time in Patent Office: Days
• US Class Current: 713/501
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode

Abstract

Systems and methods for managing power consumption in an integrated circuit to reduce the rate of change of current (di/dt) in the integrated circuit. One embodiment comprises a system having multiple processor cores. A timing system provides each of the processor cores with a corresponding operating clock signal. The timing system uses variable delay elements to impart variable delays to the clock signals. A delay management unit determines the delays that should be used by the task processing units in executing their assigned tasks and provides this information to the variable delay elements to set the appropriate delays in each of these elements. The delay information is also provided to a task management unit, which assigns the tasks to specific processor cores based upon the delays selected by the delay management unit, so that consecutively fired processor cores are not adjacent to each other.

Claims

1. A system comprising:

two or more task processing units configured to perform assigned tasks; and

a timing system configured to provide each of the task processing units with a corresponding operating clock signal;

wherein each task processing unit is configured to perform assigned tasks with timing defined by the corresponding operating clock signal; and

wherein the timing system is configured to impart variable delays to one or more of the clock signals.

2. The system of claim 1, wherein the timing system includes one or more variable delay elements, wherein each variable delay element is coupled to a corresponding one of the task processing units and is configured to delay a system clock signal by a variable amount to generate a corresponding one of the operating clock signals.

3. The system of claim 2, wherein each delay element is configured to enable selection of one of a set of discrete delays.

4. The system of claim 1, wherein the task processing units comprise processor cores in a multiprocessor system.

5. The system of claim 1, further comprising a delay management unit coupled to the timing system, wherein the delay management unit is configured to receive task information associated with a set of tasks to be performed by the task processing units, to determine desired delays for each of the operating clock signals based on the task information, and to provide information identifying the desired delays to the timing system.

6. The system of claim 5, wherein the delay management unit is configured to determine desired delays for each of the operating clock signals by identifying an entry in a look-up table corresponding to the received task information, and retrieving the information identifying the desired delays from the look-up table.

7. The system of claim 1, wherein the timing system is configured to impart delays to the clock signals such that, when the clock signals are ordered according to the magnitudes of the corresponding delays, consecutive clock signals are provided to non-adjacent task processing units.

8. A method comprising:

selecting two or more tasks for execution on corresponding task processing units;

providing each of the task processing units with a corresponding operating clock signal;

determining, based on the tasks, delays corresponding to each of the tasks;

imparting each of the delays to a corresponding one of the operating clock signals based on which of the tasks is assigned to the task processor using the operating clock signal; and

performing the tasks on the task processors according to the corresponding operating clock signals.

9. The method of claim 8, wherein imparting the delay to the corresponding one of the operating clock signals comprises providing a system clock signal to a variable delay element and outputting the operating clock signal from the variable delay element.

10. The method of claim 9, wherein imparting the delay to the corresponding one of the operating clock signals further comprises controlling the variable delay element to select one of a set of discrete delays.

11. The method of claim 8, wherein the method is implemented in a multiprocessor system and wherein the task processing units comprise processor cores.

12. The method of claim 11, wherein determining delays corresponding to each of the tasks comprises identifying an entry in a look-up table corresponding to the selected tasks and retrieving the information identifying the delays from the look-up table.

13. A system comprising:

two or more task processing units configured to perform assigned tasks; and

a timing system configured to provide each of the task processing units with a corresponding operating clock signal;

wherein each task processing unit is configured to perform assigned tasks with timing defined by the corresponding operating clock signal; and

wherein the timing system is configured to impart delays to one or more of the clock signals such that, when the clock signals are ordered according to the magnitudes of the corresponding delays, consecutive clock signals are provided to non-adjacent task processing units.

14. The system of claim 13, wherein the task processing units comprise processor cores in a multiprocessor system.

15. The system of claim 13, further comprising a task management unit, wherein the task management unit is configured to:

determine a set of tasks to be performed by the task processing units;

receive information indicating clock signal delays associated with each task in the set of tasks; and

assign each task in the set of tasks to a corresponding one of the task processing units such that, when the clock signals delays are ordered by magnitude, consecutive clock signal delays are associated with non-adjacent task processing units.

16. The system of claim 15, further comprising a delay management unit coupled to the timing system, wherein the delay management unit is configured to receive task information associated with a set of tasks to be performed by the task processing units, to determine desired delays for each of the operating clock signals based on the task information, and to provide information identifying the desired delays to the timing system.

17. The system of claim 16, wherein the delay management unit is configured to determine desired delays for each of the operating clock signals by identifying an entry in a look-up table corresponding to the received task information, and retrieving the information identifying the desired delays from the look-up table.

18. A method comprising:

selecting two or more tasks for execution on corresponding task processing units;

providing each of the task processing units with a corresponding operating clock signal; and

imparting delays to corresponding ones of the operating clock signals such that, when the clock signals are ordered according to the magnitudes of the corresponding delays, consecutive clock signals are provided to non-adjacent task processing units.

19. The method of claim 18, wherein the delays are variable, the method further comprising determining, based on the tasks, delays corresponding to each of the tasks and imparting the delay corresponding to each task to the task processing unit to be executed on the task processing unit.

20. The method of claim 19, wherein determining delays corresponding to each of the tasks comprises identifying an entry in a look-up table corresponding to the selected tasks and retrieving the information identifying the delays from the look-up table.