Method for robust statistical semiconductor device modeling

• US 20080141189A1
• Filed: 12/08/2006
• Published: 06/12/2008
• Est. Priority Date: 12/08/2006
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wason, Vineet, Goo, Jung-Suk, Wu, Zhi-Yuan, Thuruthiyil, Ciby T.
• Granted Patent: US 8,275,596 B2
• Time in Patent Office: Days
• US Class Current: 716/4
• CPC Class Codes: G06F 2111/08 Probabilistic or stochastic CAD
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

According to one exemplary embodiment, a method for robust statistical semiconductor device modeling includes building a semiconductor device model using at least one new device parameter variation, constructing a variation library for the semiconductor device model, and verifying the variation library against measured data from physical semiconductor devices. The variation library is constructed by determining variations of the at least one new device parameter variation and standard device parameters as functions of, for example, sizes and locations of semiconductor devices on semiconductor dies.

Claims

1. A method for robust statistical semiconductor device modeling, said method comprising the steps of:

building a semiconductor device model using at least one new device parameter variation;

constructing a variation library for said semiconductor device model;

verifying said variation library against measured data from a physical semiconductor device.

2. The method of claim 1 further comprising using said semiconductor device model and said variation library to fabricate a semiconductor die.

3. The method of claim 1 further comprising using said semiconductor device model and said variation library to simulate performance of a semiconductor die.

4. The method of claim 1 wherein said constructing step comprises determining variations in said at least one new device parameter variation as a function of a size of said physical semiconductor device.

5. The method of claim 1 wherein said constructing step comprises determining variations in said at least one new device parameter variation as a function of a location of said physical semiconductor device on a semiconductor die.

6. The method of claim 1 wherein said semiconductor device model includes at least one standard device parameter.

7. The method of claim 6 wherein said constructing step comprises determining variations in said at least one standard device parameter as a function of a size of said physical semiconductor device.

8. The method of claim 6 wherein said constructing step comprises determining variations in said at least one standard device parameter as a function of a location of said physical semiconductor device on a semiconductor die.

9. The method of claim 1 wherein said measured data comprises electrical parameters of said physical semiconductor device.

10. The method of claim 1 wherein said physical semiconductor device is a FET.

11. The method of claim 10 wherein said at least one new device parameter variation is selected from the group consisting of parameters related to a work function variation, a line edge roughness, and a random dopant fluctuation.

12. The method of claim 10 wherein said semiconductor device model includes at least one standard parameter selected from the group consisting of a channel length, a channel width, and a threshold voltage.

13. The method of claim 10 wherein said measured data comprises at least one electrical parameter of said FET, wherein said at least one electrical parameter is selected from the group consisting of a saturation current, a linear current, and a saturation threshold voltage.

14. A computer-readable medium containing program code for executing the method of claim 1.

15. A computer-readable medium containing program code for executing the method of claim 1, said computer-readable medium being selected from the group consisting of a compact disk (CD), a digital video disk (DVD), a flash memory storage device, a hard disk, a random access memory (RAM), and a read only memory (ROM).

16. A computer programmed with code to execute a method for robust statistical semiconductor device modeling, said method comprising the steps of:

building a semiconductor device model using at least one new device parameter variation;

constructing a variation library for said semiconductor device model;

verifying said variation library against measured data from a physical semiconductor device.

17. The computer of claim 16 wherein said computer controls an automated test equipment.

18. A system for obtaining a set of measured data from a wafer under test, said wafer under test including a physical semiconductor device, said set of measured data being utilized to implement a method for robust statistical semiconductor device modeling, said method comprising the steps of:

building a semiconductor device model using at least one new device parameter variation;

constructing a variation library for said semiconductor device model;

verifying said variation library against measured data from said physical semiconductor device.

19. The system of claim 18, wherein said method further comprises using said semiconductor device model and said variation library to fabricate a production die.

20. The system of claim 18 wherein said method further comprises using said semiconductor device model and said variation library to simulate performance of a production die.