THIN FILM TRANSISTOR AND FABRICATION METHOD THEREOF

• US 20080142808A1
• Filed: 12/12/2007
• Published: 06/19/2008
• Est. Priority Date: 12/19/2006
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung SDI Company Limited
• Inventors: LEE, Hong-Ro
• Granted Patent: US 8,097,883 B2
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30

Abstract

A thin film transistor and a fabrication method thereof, in which one excimer laser annealing (ELA) makes a pixel portion and a driver portion different from each other in surface roughness and grain size. The thin film transistor includes: a substrate including a pixel portion and a driver portion; a first semiconductor layer disposed in the pixel portion and having a first surface roughness; a second semiconductor layer disposed in the driver portion and having a second surface roughness smaller than the first surface roughness; a gate insulating layer formed on the substrate including the first and second semiconductor layers; a first gate electrode placed to correspond to the first semiconductor layer on the gate insulating layer; a second gate electrode placed to correspond to the second semiconductor layer on the gate insulating layer; an interlayer insulating layer formed on the substrate including the first and second gate electrodes; first source and drain electrodes formed on the interlayer insulating layer and electrically connected with the first semiconductor layer; and second source and drain electrodes formed on the interlayer insulating layer and electrically connected with the second semiconductor layer.

Claims

1. A thin film transistor comprising:

a substrate including a pixel portion and a driver portion;

a first semiconductor layer disposed in the pixel portion and having a first surface roughness;

a second semiconductor layer disposed in the driver portion and having a second surface roughness larger than the first surface roughness;

a first gate electrode disposed to correspond to the first semiconductor layer;

a second gate electrode disposed to correspond to the second semiconductor layer;

a gate insulating layer disposed between the first and second semiconductor layers and the first and second gate electrodes;

first source and drain electrodes electrically connected to source and drain regions of the first semiconductor layer; and

second source and drain electrodes electrically connected to source and drain regions of the second semiconductor layer.

2. The thin film transistor according to claim 1, wherein a root mean square (RMS) ratio of the first surface roughness to the second surface roughness is 25˜

90%.

3. The thin film transistor according to claim 2, wherein the first surface roughness is 18˜

270 Å

.

4. The thin film transistor according to claim 2, wherein the second surface roughness is 20˜

300 Å

.

5. The thin film transistor according to claim 1, wherein the first and second gate electrodes include a molybdenum-tungsten (MoW) alloy.

6. A method of fabricating a thin film transistor, comprising:

providing a substrate including a pixel portion and a driver portion;

forming an amorphous silicon layer on the substrate;

forming a polycrystalline silicon layer by sequentially scanning a laser beam on the amorphous silicon layer in the pixel portion while moving the laser beam at a first scan pitch;

forming a polycrystalline silicon layer by sequentially scanning the laser beam on the amorphous silicon layer in the driver portion while moving the laser beam at a second scan pitch smaller than the first scan pitch;

patterning the polycrystalline silicon layer to form a first semiconductor layer having a first surface roughness in the pixel portion and a second semiconductor layer having a second surface roughness larger than the first surface roughness in the driver portion;

forming a gate insulating layer on the substrate including the first and second semiconductor layers;

forming first and second gate electrodes on the gate insulating layer to correspond to the first and second semiconductor layers;

forming first and second source and drain regions by implanting an impurity ion into the first and second semiconductor layers;

forming an interlayer insulating layer on the substrate including the first and second gate electrodes; and

forming first and second source and drain electrodes on the interlayer insulating layer, the first and second source and drain electrodes being electrically connected with the first and second source and drain regions, respectively.

7. The method according to claim 6, wherein the polycrystalline silicon layer is formed by excimer laser annealing (ELA).

8. The method according to claim 6, wherein the first scan pitch is 1.25˜

7.5% of a width of the laser beam.

9. The method according to claim 6, wherein a root mean square (RMS) ratio of the first surface roughness to the second surface roughness is 25˜

90%.

10. The method according to claim 8, wherein the second scan pitch is 10˜

80% of the first scan pitch.

11. The method according to claim 8, wherein the first scan pitch is 5˜

30 μ

m.

12. The method according to claim 10, wherein the second scan pitch is 4˜

24 μ

m.

13. The method according to claim 9, wherein the first surface roughness is 18˜

270 Å

.

14. The method according to claim 9, wherein the second surface roughness is 20˜

300 Å

.

15. The method according to claim 6, wherein the first and second scan pitches depend on a stage moving speed divided by an oscillation frequency of the laser beam.

16. A method of fabricating a thin film transistor, comprising:

providing a substrate including a pixel portion and a driver portion;

forming an amorphous silicon layer on the substrate;

crystallizing the amorphous silicon layer disposed above the pixel portion into a first polycrystalline silicon layer having a first surface roughness and crystallizing the amorphous silicon layer disposed above the driver portion into a second polycrystalline silicon layer having a second surface roughness greater than the first surface roughness;

wherein the amorphous silicon layer disposed above the pixel portion and the driver portion is crystallized into the first and second polycrystalline silicon layers in a one scanning process.

17. The method according to claim 16, wherein the first and second polycrystalline silicon layers are formed by excimer laser annealing (ELA).

18. The method according to claim 16, wherein a root mean square (RMS) ratio of the first surface roughness to the second surface roughness is 25˜

90%.

19. The method according to claim 16, wherein the first surface roughness is 18˜

270 Å

.

20. The method according to claim 16, wherein the second surface roughness is 20˜

300 Å

.