Transistors

• US 20080142882A1
• Filed: 02/15/2008
• Published: 06/19/2008
• Est. Priority Date: 09/01/2004
• Status: Active Grant

• Current Assignee: Gordon A. Haller, Kris K. Brown, Sanh D. Tang, Tuman Earl Allen
• Original Assignee: Gordon A. Haller, Kris K. Brown, Sanh D. Tang, Tuman Earl Allen
• Inventors: Tang, Sanh D., Allen, Tuman Earl, Haller, Gordon, Brown, Kris K.
• Granted Patent: US 7,825,462 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

Claims

1-40. -40. (canceled)

41. A transistor comprising:

a semiconductive substrate;

a gate extending within the semiconductive substrate; and

a pair of source/drain regions proximate the gate, a first source/drain region of the pair comprising a portion of the semiconductive substrate, a second source/drain region of the pair comprising material other than the semiconductive substrate.

42. The transistor of claim 41 wherein the first source/drain region comprises a diffusion region in the semiconductive substrate.

43. The transistor of claim 41 wherein the second source/drain region comprises conductive material over the semiconductive substrate.

44. The transistor of claim 41 wherein the second source/drain region comprises doped polysilicon over the semiconductive substrate.

45. The transistor of claim 41 wherein the gate comprises an upper surface, and wherein each of the pair of the source/drain regions comprises uppermost surfaces elevationally above the upper surface of the gate.

46. The transistor of claim 41 wherein the second source/drain region comprises a cylindrical configuration.

47. A transistor comprising:

a semiconductive substrate comprising an upper surface;

a gate extending within the semiconductive substrate; and

a pair of source/drain regions proximate the gate, at least one of the pair of the source/drain regions extends outwardly from the upper surface of the semiconductive substrate.

48. The transistor of claim 47 wherein the one source/drain region comprises a height dimension of about 1,000 to about 1,500 angstroms.

49. The transistor of claim 47 wherein the one source/drain region comprises epitaxial silicon.

50. The transistor of claim 47 wherein an entirety of the one source/drain region extends outwardly from the upper surface of the semiconductive substrate.

51. The transistor of claim 47 wherein only a first portion of the one source/drain region extends outwardly from the upper surface of the semiconductive substrate, and wherein a second portion of the one source/drain region extends into the semiconductive substrate from the upper surface.

52. The transistor of claim 51 wherein the second portion of the one source/drain region comprises material of the semiconductive substrate, and wherein the first portion of the one source/drain region comprises material other than the material of the semiconductive substrate.

53. A transistor comprising:

a longitudinally-extending gate layer;

a first source/drain region oriented laterally of the gate layer; and

a second source/drain region insulated from and extending within the longitudinally-extending gate layer.

54. The transistor of claim 53 wherein the gate layer comprises an upper surface, and wherein the first and the second source/drain regions each comprises uppermost surfaces that are approximately parallel with the upper surface of the gate layer.

55. The transistor of claim 53 wherein the first source/drain region is oriented laterally a first side of the gate layer, and further comprising a third source/drain region oriented laterally a second side of the gate layer, the second side opposite the first side of the gate layer.

56. The transistor of claim 55 wherein the first source/drain region comprises a structural configuration that is substantially the same as a structural configuration of the third source/drain region.

57. The transistor of claim 55 wherein the second source/drain region comprises a structural configuration that is substantially different from structural configurations of the first and the third source/drain regions.