INTEGRATED CIRCUIT SYSTEM HAVING STRAINED TRANSISTOR

• US 20080142897A1
• Filed: 12/19/2006
• Published: 06/19/2008
• Est. Priority Date: 12/19/2006
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG, International Business Machines Corporation, Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC), Samsung Electronics Co. Ltd.
• Original Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG), International Business Machines Corporation, Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC), Samsung Electronics Co. Ltd.
• Inventors: Teh, Young Way, Chen, Xiangdong, Belyansky, Michael P., Knoefler, Roman, Yang, Daewon, Kim, Jun Jung, Fen, Jamin F.
• Application Number:
  US11/613,149
• Publication Number:
  US 20080142897A1
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

An integrated circuit system is provided including forming a circuit element on a wafer, forming a stress formation layer having a non-uniform profile over the wafer, and forming an interlayer dielectric over the stress formation layer and the wafer.

Claims

1. An integrated circuit system comprising:

forming a circuit element on a wafer;

forming a stress formation layer having a non-uniform profile over the wafer; and

forming an interlayer dielectric over the stress formation layer and the wafer.

2. The system as claimed in claim 1 wherein:

forming the circuit element on the wafer includes;

forming a gate stack of the circuit element; and

forming the stress formation layer having the non-uniform profile further includes;

forming the stress formation layer, having the non-uniform profile, with a mimimal amount thereof along a vertical side of the gate stack.

3. The system as claimed in claim 1 wherein:

forming the circuit element on the wafer includes;

forming a gate stack of the circuit element, and

forming a spacer along a vertical side of the gate stack; and

forming the stress formation layer having the non-uniform profile further includes;

forming the stress formation layer, having the non-uniform profile, with a mimimal amount thereof over the spacer.

4. The system as claimed in claim 1 wherein forming the interlayer dielectric includes forming the interlayer dielectric substantially without voids.

5. The system as claimed in claim 1 wherein forming the stress formation layer includes forming a layer comprised of a compression stressed material.

6. An integrated circuit system comprising:

forming a first transistor and a second transistor on a wafer;

high density plasma depositing a stress formation layer, having a non-uniform profile, comprised of nitride over the first transistor, the second transistor, and the wafer;

forming an interdielectric oxide layer over the stress formation layer, the first transistor, the second transistor, and the wafer.

7. The system as claimed in claim 6 wherein forming the first transistor and the second transistor includes forming p-type transistors.

8. The system as claimed in claim 6 wherein:

forming the first transistor and the second transistor on the wafer includes;

forming a first gate stack of the first transistor,

forming a second gate stack of the second transistor; and

high density plasma depositing the stress formation layer, having the non-uniform profile, further includes;

forming the stress formation layer, having the non-uniform profile, with a mimimal amount thereof along a vertical side of the first gate stack and the second gate stack for space reduction between the first transistor and the second transistor.

9. The system as claimed in claim 6 wherein:

forming the first transistor and the second transistor includes;

forming a first gate stack, a first source region, and a first drain region of the first transistor,

forming a second gate stack, a second source region, and a second drain region of the second transistor; and

high density plasma depositing the stress formation layer, having the non-uniform profile, further includes;

forming the stress formation layer, having the non-uniform profile, over the first gate stack, the first source region, the first drain region, the second gate stack, the second source region, and the second drain region.

10. The system as claimed in claim 6 wherein forming the first transistor and the second transistor includes forming complementary metal oxide semiconductor transistors.

11. An integrated circuit system comprising:

a circuit element on a wafer;

a stress formation layer having a non-uniform profile over the wafer; and

an interlayer dielectric over the stress formation layer and the wafer.

12. The system as claimed in claim 11 wherein:

the circuit element has a gate stack on the wafer; and

the stress formation layer, having the non-uniform profile, has mimimal amount along a vertical side of the gate stack over the wafer.

13. The system as claimed in claim 11 wherein:

the circuit element on the wafer includes;

a gate stack of the circuit element, and

a spacer along a vertical side of the gate stack; and

the stress formation layer having the non-uniform profile further includes;

the stress formation layer, having the non-uniform profile, with a mimimal amount thereof over the spacer.

14. The system as claimed in claim 11 wherein the interlayer dielectric is substantially without voids.

15. The system as claimed in claim 11 wherein the stress formation layer is comprised of a compression stressed material.

16. The system as claimed in claim 11 wherein:

the circuit element includes a first transistor and a second transistor on the wafer;

the stress formation layer, having the non-uniform profile, is comprised of nitride over the first transistor, the second transistor, and the wafer; and

an interlayer dielectric is an interdielectric oxide layer over the stress formation layer, the first transistor, the second transistor, and the wafer.

17. The system as claimed in claim 16 wherein the first transistor and the second transistor are p-type transistors.

18. The system as claimed in claim 16 wherein:

the first transistor and the second transistor on the wafer includes;

a first gate stack of the first transistor,

a second gate stack of the second transistor; and

the stress formation layer, having the non-uniform profile, further includes;

the stress formation layer, having the non-uniform profile, with a mimimal amount thereof along a vertical side of the first gate stack and the second gate stack for space reduction between the first transistor and the second transistor.

19. The system as claimed in claim 16 wherein:

the first transistor and the second transistor includes;

a first gate stack, a first source region, and a first drain region of the first transistor,

a second gate stack, a second source region, and a second drain region of the second transistor; and

the stress formation layer, having the non-uniform profile, is over the first gate stack, the first source region, the first drain region, the second gate stack, the second source region, and the second drain region.

20. The system as claimed in claim 16 wherein the first transistor and the second transistor includes forming complementary metal oxide semiconductor transistors.