INTEGRATED CIRCUIT SYSTEM HAVING STRAINED TRANSISTOR
First Claim
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1. An integrated circuit system comprising:
- forming a circuit element on a wafer;
forming a stress formation layer having a non-uniform profile over the wafer; and
forming an interlayer dielectric over the stress formation layer and the wafer.
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Abstract
An integrated circuit system is provided including forming a circuit element on a wafer, forming a stress formation layer having a non-uniform profile over the wafer, and forming an interlayer dielectric over the stress formation layer and the wafer.
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Citations
20 Claims
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1. An integrated circuit system comprising:
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forming a circuit element on a wafer; forming a stress formation layer having a non-uniform profile over the wafer; and forming an interlayer dielectric over the stress formation layer and the wafer. - View Dependent Claims (2, 3, 4, 5)
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6. An integrated circuit system comprising:
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forming a first transistor and a second transistor on a wafer; high density plasma depositing a stress formation layer, having a non-uniform profile, comprised of nitride over the first transistor, the second transistor, and the wafer; forming an interdielectric oxide layer over the stress formation layer, the first transistor, the second transistor, and the wafer. - View Dependent Claims (7, 8, 9, 10)
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11. An integrated circuit system comprising:
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a circuit element on a wafer; a stress formation layer having a non-uniform profile over the wafer; and an interlayer dielectric over the stress formation layer and the wafer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification