Method and Structure for Optimizing Yield of 3-D Chip Manufacture

• US 20080142959A1
• Filed: 02/11/2008
• Published: 06/19/2008
• Est. Priority Date: 10/11/2005
• Status: Active Grant

• Current Assignee: Albert M. Young, Edward M. Demulder, Michael J. Shapiro, Sarah H. Knickerbocker
• Original Assignee: Albert M. Young, Edward M. Demulder, Michael J. Shapiro, Sarah H. Knickerbocker
• Inventors: Young, Albert M., Shapiro, Michael J., DeMulder, Edward M., Knickerbocker, Sarah H.
• Granted Patent: US 7,999,377 B2
• Time in Patent Office: Days
• US Class Current: 257/723
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout

Abstract

The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.

Claims

1-18. -18. (canceled)

19. A 3-D integrated semiconductor structure comprising:

first and second semiconductor chips, each having at least one capture pad deposited on at least one side, wherein said first and second semiconductor chips are oriented such that said sides containing said at least one capture pad are internally positioned and face one another;

a handle wafer chip attached to the side of each first semiconductor chip opposite of said side containing said at least one capture pad; and

a wafer housing said second semiconductor chips, each second semiconductor chip having been tested, whereon at least one capture pad of said first semiconductor chips is bonded to at least one capture pad of said second semiconductors chips tested and determined to be functioning.

20. A 3-D integrated semiconductor structure as recited in claim 19, wherein said at least one capture pad has a thickness in the range of one micron to one hundred microns.

21. A 3-D integrated semiconductor structure as recited in claim 20, wherein said at least one capture pad has a thickness in the range of ten microns to fifty microns.

22. A 3-D integrated semiconductor structure as recited in claim 19, wherein said at least one capture pad included at least one metal selected from the group consisting of copper, tin, gold and aluminum.

23. A 3-D integrated semiconductor structure as recited in claim 19, wherein said first semiconductor chip is a thinned semiconductor chip.

24. A 3-D integrated semiconductor structure as recited in claim 23, wherein said first semiconductor chip includes vias.

25. A 3-D integrated semiconductor structure as recited in claim 24, wherein said vias contain metal.