On Silicon Interconnect Capacitance Extraction

• US 20080143348A1
• Filed: 12/19/2005
• Published: 06/19/2008
• Est. Priority Date: 12/23/2004
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Wieling, Jean, Pavithran, Praveen, Veendrick, Hendricus Joseph, Pelgrom, Marcel
• Granted Patent: US 7,791,357 B2
• Time in Patent Office: Days
• US Class Current: 324/683
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66

Abstract

The present invention relates to a on-chip circuit for on silicon interconnect capacitance (Cx) extraction that is self compensated for process variations in the integrated transistors. The circuit (10) comprises signal generation means (20) for generating a periodical pulse signal connected to first and to second signal delaying means (31, 32) for respective delaying said pulse signal, wherein said second signal delaying means (32) are configured to have a delay affected by said interconnect capacitance (Cx); a logical XOR gate (35) for connecting respective first and said second delay signals of said respective first and second delay means (31, 32), said logical XOR gate (35) being connected to signal integrating means (40); and said signal integrating means (40) being connected to analog to digital converting means (50). Whilst the error in conventional uncompensated systems, like delay line only, the error can be up to 30%, in the circuit according to the invention, the error due to process variations in the front-end is about 2%. Further, an output is provided in a digital format and thus, can be measured quickly with simple external hardware. Furthermore, the pulse signal frequency can be used as a monitor to measure process variations in the front-end. Moreover, since the circuit (10) is remarkably accurate and very easy to measure, it is the best choice as a process monitor for every chip fabricated in the future.

Claims

1. A circuit for interconnect capacitance measurement integrated on a semiconductor chip comprising:

signal generation means for generating a periodical pulse signal connected to a first and to a second signal delaying means for respective delaying said pulse signal, wherein said second signal delaying means are configured to have a delay affected by said interconnect capacitance;

a logical XOR gate means by for connecting respective first and said second delay signals of said respective first and second delay means, said logical XOR gate means being connected to signal integrating means; and

said signal integrating means being connected to analog to digital converting means.

2. The circuit according to claim 1, further comprises frequency counting means connected to said signal generation means.

3. The circuit according to claim 1, wherein said signal generation means comprising a logical NAND gate means and a feed-back loop with a first even number of consecutive connected logical gate elements.

4. The circuit according to claim 1, wherein each of said first and second delay means comprise a second even number of consecutive connected logical gate elements, said logical gate elements of said second delay means being loaded at respective outputs with said capacitance.

5. The circuit according to claim 4, wherein each of said first and second delay means further comprise an additional logical gate element interconnected between said respective delay means and said logical XOR gate means.