High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion

• US 20080143385A1
• Filed: 11/27/2007
• Published: 06/19/2008
• Est. Priority Date: 05/22/2003
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Alan Refalo, Greg J. Landry, Jeyenth Vijayaraghavan, Sherif Hanna
• Inventors: Hanna, Sherif, Vijayaraghavan, Jeyenth, Landry, Greg J., ReFalo, Alan
• Granted Patent: US 7,777,521 B2
• Time in Patent Office: Days
• US Class Current: 326/68
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors

Abstract

Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is included to receive the resulting signals and to provide increased swing signals. A CMOS buffer is also included and is configured to receive the increased swing signals and to provide a CMOS logic output. Also disclosed is a method of translating a differential logic signal to a CMOS logic signal including level-shifting and buffering differential input signals to provide resulting signals with lower common mode voltage. The method also includes using a gain stage to provide increased swing signals from the resulting lower common mode signals and using a CMOS buffer to provide a CMOS output from the increased swing signals.

Claims

1. A translator for translating differential input signals into a CMOS logic output, comprising:

a level-shifting and buffering stage configured to receive the differential input signals and to provide a set of level shifted signals;

a gain stage configured to receive the set of level shifted signals and to provide a set of increased swing signals; and

a CMOS buffer configured to receive the set of increased swing signals and to provide a CMOS logic output.

2. The translator of claim 1, wherein the level-shifting and buffering stage comprises:

a first passively-loaded differential structure configured to receive the differential input signals and to provide a set of intermediate level shifted signals; and

a second passively-loaded differential structure configured to receive the set of intermediate level shifted signals and to provide the set of level shifted signals.

3. The translator of claim 1, wherein the level shifting and buffering stage includes a first buffer receiving the differential input signals and a second buffer, said second buffer receiving an output from the first buffer.

4. The translator of claim 3, wherein the first buffer includes:

a first transistor receiving a first input signal of said differential input signals;

a second transistor receiving a second input signal of said differential input signals, the first transistor and the second transistor connected in parallel at a node; and

a third transistor connected between the node and ground.

5. The translator of claim 4, wherein the first and second transistors are n-channel transistors.

6. The translator of claim 4, wherein the first buffer includes at least one pull-up resistor, and

wherein the first and second transistors are coupled with the at least one pull-up resistors.

7. The translator of claim 1, wherein the gain stage includes:

one or more cross-coupled inverters coupled with the set of level shifted signals.

8. The translator of claim 1, further comprising:

a pair of CMOS inverters receiving the set of increased swing signals, said CMOS inverters bringing the set of increased swing signals to CMOS logic voltage levels.

9. The translator of claim 1, wherein the CMOS buffer includes:

a pull-down path receiving a first of said set of increased swing signals; and

a pull-up path receiving a second of said set of increased swing signals, said pull-down path and said pull-up path coupled together to form the CMOS logic output.

10. The translator of claim 9, wherein the pull-down path includes:

a first transistor and a second transistor connected in series, the first transistor coupled between a supply voltage and the second transistor, the second transistor coupled between ground and the first transistor, both the first and second transistors controlled by the first of said set of increased swing signals.

11. The translator of claim 10, wherein the pull-up path includes:

a third transistor and a fourth transistor connected in series, the third transistor coupled between a supply voltage and the fourth transistor, the fourth transistor coupled between ground and the third transistor.

12. The translator of claim 10, wherein the first transistor is a p-channel transistor.

13. The translator of claim 1, further comprising:

means for reducing signal skew within the CMOS buffer.

14. A method of translating a differential logic signal to a CMOS logic signal, including:

buffering the differential logic input signal to provide a set of reduced common mode signals;

providing a gain stage to form a set of increased swing signals from the set of reduced common mode signals; and

providing a CMOS buffer to form the CMOS output signal from the set of increased swing signals.

15. The method of claim 14, wherein the buffering operation includes providing a first and second buffer in series.

16. The method of claim 14, further comprising:

reducing signal skew within the CMOS buffer.

17. An integrated circuit, comprising:

at least one set differential logic signals;

a translator for translating the at least one set of differential logic signals into a CMOS logic signal, the translator comprising;

a buffering and level shifting stage configured to receive the at least one set of differential logic signals and to provide a first output;

a gain stage coupled with the first output and providing a second output; and

a CMOS buffer stage coupled with the second output and providing the CMOS logic signal.

18. The integrated circuit of claim 17, wherein the buffering and level shifting stage of the translator includes:

a first and second buffer coupled in series, the first buffer receiving the at least one set of differential logic signals.

19. The integrated circuit of claim 17, wherein the gain stage of the translator includes:

one or more cross-coupled inverters.

20. The integrated circuit of claim 17, wherein the CMOS buffer stage of the translator further comprises:

means for reducing signal skew within the CMOS buffer.