High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion
First Claim
1. A translator for translating differential input signals into a CMOS logic output, comprising:
- a level-shifting and buffering stage configured to receive the differential input signals and to provide a set of level shifted signals;
a gain stage configured to receive the set of level shifted signals and to provide a set of increased swing signals; and
a CMOS buffer configured to receive the set of increased swing signals and to provide a CMOS logic output.
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Accused Products
Abstract
Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is included to receive the resulting signals and to provide increased swing signals. A CMOS buffer is also included and is configured to receive the increased swing signals and to provide a CMOS logic output. Also disclosed is a method of translating a differential logic signal to a CMOS logic signal including level-shifting and buffering differential input signals to provide resulting signals with lower common mode voltage. The method also includes using a gain stage to provide increased swing signals from the resulting lower common mode signals and using a CMOS buffer to provide a CMOS output from the increased swing signals.
99 Citations
20 Claims
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1. A translator for translating differential input signals into a CMOS logic output, comprising:
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a level-shifting and buffering stage configured to receive the differential input signals and to provide a set of level shifted signals; a gain stage configured to receive the set of level shifted signals and to provide a set of increased swing signals; and a CMOS buffer configured to receive the set of increased swing signals and to provide a CMOS logic output. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of translating a differential logic signal to a CMOS logic signal, including:
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buffering the differential logic input signal to provide a set of reduced common mode signals; providing a gain stage to form a set of increased swing signals from the set of reduced common mode signals; and providing a CMOS buffer to form the CMOS output signal from the set of increased swing signals. - View Dependent Claims (15, 16)
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17. An integrated circuit, comprising:
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at least one set differential logic signals; a translator for translating the at least one set of differential logic signals into a CMOS logic signal, the translator comprising; a buffering and level shifting stage configured to receive the at least one set of differential logic signals and to provide a first output; a gain stage coupled with the first output and providing a second output; and a CMOS buffer stage coupled with the second output and providing the CMOS logic signal. - View Dependent Claims (18, 19, 20)
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Specification