Apparatus and method for adjusting slew rate in semiconductor memory device

• US 20080143406A1
• Filed: 01/30/2008
• Published: 06/19/2008
• Est. Priority Date: 04/16/2004
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Im, Jae-Hyuk, Park, Kee-Teok
• Granted Patent: US 7,598,785 B2
• Time in Patent Office: Days
• US Class Current: 327/170
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing

Abstract

A slew-rate adjusting apparatus for use in a semiconductor memory device includes: a slew-rate modulation signal generator for generating a slew-rate modulation signal according to the number of control codes having a first logic level among a plurality of control codes, which are programmable at an exterior; and a pre-driver for adjusting a slew rate of a data signal by changing the number of switching elements turned on in response to the slew-rate modulation signal.

Claims

1-14. -14. (canceled)

15. A slew-rate adjusting apparatus for use in a semiconductor memory device, comprising:

a slew-rate modulation signal generator for generating a slew-rate modulation signal according to a plurality of control codes, which exclusively have a first logic level, wherein the control codes are programmable at an external; and

a pre-driver for adjusting a slew rate of a data signal according to the number of switching elements turned on in response to the slew-rate modulation signal.

16. The slew-rate adjusting apparatus as recited in claim 15, wherein the slew-rate modulation signal generator includes:

a logic level changing unit for changing logic levels of the control codes and outputting a control signal; and

a switching unit for generating the slew-rate modulation signal used to select the switching elements turned on in response to the control signal.

17. The slew-rate adjusting apparatus as recited in claim 15, wherein the pre-driver includes:

an upper pre-driver having a plurality of switching elements connected in parallel with a ground voltage terminal; and

a lower pre-driver having a plurality of switching elements connected in parallel with a driving voltage terminal.

18. The slew-rate adjusting apparatus as recited in claim 17, wherein the plurality of switching elements included in the upper pre-driver have the same size.

19. The slew-rate adjusting apparatus as recited in claim 16, wherein the logic level changing unit includes:

a first inverter for inverting the first control code;

a second inverter for inverting the second control code; and

a third inverter for inverting the third control code.

20. The slew-rate adjusting apparatus as recited in claim 19, wherein the switching unit includes:

a first PMOS transistor configured to be turned on in response to an output of the first inverter;

a second PMOS transistor configured to be turned on in response to an output of the second inverter;

a third PMOS transistor configured to be turned on in response to an output of the third inverter;

a first NMOS transistor configured to be turned on in response to the first control code;

a second NMOS transistor configured to be turned on in response to the second control code; and

a third NMOS transistor configured to be turned on in response to the third control code.

21. A slew-rate adjusting apparatus for use in a semiconductor memory device, comprising:

a slew-rate modulation signal generator for generating a slew-rate modulation signal according to a plurality of control codes and inverted signals of the control codes, wherein the control codes are programmable at an external; and

a pre-driver for changing the number of switching elements turned on in response to the slew-rate modulation signal, thereby adjusting a slew rate of a data signal.

22. The slew-rate adjusting apparatus as recited in claim 21, wherein the slew-rate modulation signal generator includes a plurality of inverters for inverting the plurality of the control codes.

23. The slew-rate adjusting apparatus as recited in claim 22, wherein the pre-driver includes:

an upper pre-driver for adjusting a slew rate of an upper data signal in response to the plurality of the control codes; and

a lower pre-driver for adjusting a slew rate of a lower data signal in response to output signals of the plurality of the inverters.

24. The slew-rate adjusting apparatus as recited in claim 23, wherein the upper pre-driver includes:

a first resistor group having a plurality of resistors connected in series; and

a first switching element group controlled by the plurality of control codes and connected in parallel with the resistors of the first resistor group.

25. The slew-rate adjusting apparatus as recited in claim 24, wherein the resistors of the first resistor group have an electrically equal size to one another.

26. The slew-rate adjusting apparatus as recited in claim 25, wherein the lower pre-driver includes:

a second resistor group having a plurality of resistors connected in series; and

a second switching element group controlled by the output signals of the plurality of the inverters and connected in parallel with the resistors of the second resistor group.

27. A slew-rate adjusting apparatus for use in a semiconductor memory device, comprising:

a slew-rate modulation signal generator for generating a slew-rate modulation signal according to a plurality of control codes and inverted signals of the control codes, wherein the control codes are programmable at an exterior; and

a pre-driver for adjusting a slew rate of a data signal according to size of switching elements turned on in response to the slew-rate modulation signal.

28. The slew-rate adjusting apparatus as recited in claim 27, wherein the slew-rate modulation signal generator includes a plurality of inverters for inverting the plurality of the control codes.

29. The slew-rate adjusting apparatus as recited in claim 27, wherein the pre-driver includes:

an upper pre-driver for adjusting a slew rate of an upper data signal in response to the plurality of the control codes; and

a lower pre-driver for adjusting a slew rate of a lower data signal in response to the output signals of the plurality of the inverters.

30. The slew-rate adjusting apparatus as recited in claim 29, wherein the upper pre-driver includes:

a first resistor group having a plurality of resistors connected in series; and

a first switching element group controlled by the plurality of the control codes and connected in parallel with the resistors of the first resistor group.

31. The slew-rate adjusting apparatus as recited in claim 30, wherein the resistors of the first resistor group have an electrically different size from one another.

32. The slew-rate adjusting apparatus as recited in claim 31, wherein the lower pre-driver includes:

a second resistor group having a plurality of resistors connected in series; and

a second switching element group controlled by the output signals of the plurality of the inverters and connected in parallel with the resistors of the second resistor group.