Signal generating circuit

• US 20080143407A1
• Filed: 12/19/2006
• Published: 06/19/2008
• Est. Priority Date: 12/19/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Paillet, Fabrice, Schrom, Gerhard, Hazucha, Peter, Karnik, Tanay, Somasekhar, Dinesh, Moon, Sung Tae
• Granted Patent: US 7,602,257 B2
• Time in Patent Office: Days
• US Class Current: 327/172
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/151 with two complementary outputs
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation

Abstract

Embodiments of a signal generating circuit are generally described herein. Other embodiments may be described and claimed.

Claims

1. A signal generating circuit comprising:

a ring oscillator having a plurality of delay circuits coupled in series, each delay circuit to provide a control signal; and

a weighted-sum circuit to receive an offset voltage and the plurality of control signals and to provide an output analog signal.

2. The signal generating circuit of claim 1, further comprising a comparator to compare the output analog signal with a threshold voltage and to provide a pulse width modulated (PWM) signal.

3. The signal generating circuit of claim 1, wherein the output analog signal comprises a triangular signal.

4. The signal generating circuit of claim 1, wherein the output analog signal comprises a sinusoidal signal.

5. The signal generating circuit of claim 1, wherein the weighted-sum circuit includes a first weighted-sum circuit to provide a first output analog signal and a second weighted-sum circuit to provide a second output analog signal.

6. The signal generating circuit of claim 5, wherein the second output analog signal is phase-shifted from the first output analog signal.

7. The signal generating circuit of claim 5, wherein the second output analog signal is a different type of signal than the first output analog signal.

8. The signal generating circuit of claim 1, wherein the weighted-sum circuit comprises a plurality of switch-resistor implementations.

9. The signal generating circuit of claim 8, wherein each of the switch-resistor implementations receives a separate one of the plurality of the control signals from the ring oscillator.

10. The signal generating circuit of claim 1, wherein the ring oscillator includes a plurality of switches between each of the delay circuits.

11. The signal generating circuit of claim 10, wherein each of the delay circuits is a configurable delay circuit, and the switches control a speed of the ring oscillator.

12. A signal generating circuit comprising:

a plurality of delay circuits coupled to provide a plurality of control signals;

a weighted-sum circuit to receive the plurality of control signals and to provide an output analog signal; and

a comparator circuit to compare the output analog signal with a voltage and to provide a pulse width modulated (PWM) signal based on the comparison.

13. The signal generating circuit of claim 12, wherein the output analog signal comprises a periodic signal.

14. The signal generating circuit of claim 12, wherein the weighted-sum circuit includes a first weighted-sum circuit to provide a first output analog signal and a second weighted-sum circuit to provide a second output analog signal.

15. The signal generating circuit of claim 14, wherein the second output analog signal is phase-shifted from the first output analog signal.

16. The signal generating circuit of claim 14, wherein the second output analog signal is a different type of signal than the first output analog signal.

17. The signal generating circuit of claim 12, wherein the delay circuits comprise configurable delay circuits.

18. The signal generating circuit of claim 17, further comprising switches to control speed of the plurality of delay circuits.

19. A system comprising:

a processor;

a signal generating circuit to generate a pulse width modulated signal;

a power converter circuit to receive the pulse width modulated signal and provide a signal to the processor; and

a wireless interface to link the processor to a wireless network, the signal generating circuit including;

a ring oscillator having a plurality of delay circuits to provide a plurality of control signals; and

a weighted-sum circuit to receive the plurality of control signals and to provide an output analog signal.

20. The system of claim 19, the signal generating circuit further including a comparator to compare the output analog signal with a threshold voltage and to provide a pulse width modulated (PWM) signal based on the comparison.

21. The system of claim 19, wherein the weighted-sum circuit includes a first weighted-sum circuit to provide a first output analog signal and a second weighted-sum circuit to provide a second output analog signal.

22. The system of claim 21, wherein the second output analog signal is phase-shifted from the first output analog signal.

23. The system of claim 21, wherein the second output analog signal is a different type of signal than the first output analog signal.