Systems and Methods for Providing a Shared Buffer in a Multiple FIFO Environment

• US 20080143733A1
• Filed: 12/19/2006
• Published: 06/19/2008
• Est. Priority Date: 12/19/2006
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Brothers, John
• Granted Patent: US 8,736,627 B2
• Time in Patent Office: Days
• US Class Current: 345/558
• CPC Class Codes: G06T 1/60 Memory management

Abstract

Provided are methods and systems for reducing memory bandwidth usage in a common buffer, multiple FIFO computing environment. The multiple FIFO'"'"'s are arranged in coordination with serial processing units, such as in a pipeline processing environment. The multiple FIFO'"'"'s contain pointers to entry addresses in a common buffer. Each subsequent FIFO receives only pointers that correspond to data that has not been rejected by the corresponding processing unit. Rejected pointers are moved to a free list for reallocation to later data.

Claims

1. A system for sharing a buffer in a multiple first-in-first-out (FIFO) computer graphics processing environment, comprising:

a shared buffer configured to receive a plurality of attribute values corresponding to a plurality of graphics data values;

a plurality of data processing components, organized serially in a computer graphics pipeline, configured to process the plurality of graphics data values;

a plurality of pointer arrays, organized serially in the computer graphics pipeline and configured to maintain a plurality of pointers, corresponding to the plurality of attribute values; and

a buffer mask configured to identify at least one location of available memory in the shared buffer.

2. The system of claim 1, wherein the buffer mask includes a plurality of bits corresponding to a plurality of addresses in the shared buffer.

3. The system of claim 1, wherein one of the plurality of data processing components comprises an attribute setup unit, configured to generate the plurality of attribute values, and another of the plurality of data processing components comprises a Z test unit.

4. The system of claim 3, wherein one of the plurality of pointer arrays comprises a first pointer array logically configured between the attribute setup unit and the Z test unit.

5. The system of claim 4, further comprising:

a first triangle; and

a first bit, corresponding to a first shared buffer memory address, wherein if the first triangle is rejected by the Z test unit then the first bit is written to the buffer mask.

6. The system of claim 5, further comprising a first pointer of the plurality of pointers, wherein the first pointer is discarded from the first pointer array and wherein the first pointer corresponds to the first triangle, if the first triangle is rejected by the Z test unit.

7. The system of claim 1, wherein each of the plurality of pointer arrays corresponds to two of the plurality of data processing components.

8. The system of claim 1, wherein a portion of the plurality of attribute values comprises triangle delta data wherein another portion of the plurality of attribute values comprises state data.

9. The system of claim 7, further comprising:

a triangle; and

an attribute delta data pointer, corresponding to triangle delta data of the triangle;

wherein if the triangle is rejected by one of the plurality of data processing components then the attribute delta data pointer is discarded by the one of the plurality of pointer arrays that corresponds to the one of the plurality of data processing units.

10. The system of claim 9, further comprising a state data pointer, corresponding to state data of the triangle, wherein the state data pointer is transferred to an adjacent one of the plurality of pointer arrays.

11. The system of claim 1, wherein each of the plurality of pointer arrays comprises capacity to maintain a number of pointers equal to a number of addresses in the shared buffer.

12. The system of claim 1, wherein one of the data processing components comprises an interpolation unit.

13. The system of claim 12, wherein one of the plurality of pointer arrays is configured to compensate for texture read latency and corresponds to the interpolation unit and wherein each of the plurality of pointer arrays comprises a first-in-first-out buffer.

14. A method for providing a common buffer in a computing environment having pointers in multiple first-in-first-out buffers (FIFO), comprising:

determining, in an attribute setup unit, a plurality of attribute values;

reading a free list, configured to mask unavailable addresses in a common buffer, to establish a plurality of entry addresses, in the common buffer, corresponding to the plurality of attribute values;

writing the plurality of attribute values to the plurality of entry addresses in the common buffer;

writing a plurality of pointers, corresponding to the plurality of entry addresses, to a first pointer FIFO;

tracking, in a first processing unit, a plurality of triangles to determine if any of the plurality of triangles is rejected;

copying, to the free list, a portion of the plurality of pointers corresponding to rejected triangles; and

transferring, to a second pointer FIFO, any of the plurality of pointers corresponding to triangles that are not rejected.

15. The method of claim 14, wherein the determining further comprises at least one of the following:

establishing at least one delta value as an FIFO entry and establishing at least one state value as an attribute value.

16. The method of claim 15, wherein if the portion of the plurality of pointers corresponds to the at least one state value then the corresponding one of the plurality of pointers is not copied to the free list.

17. The method of claim 15, further comprising flagging, with a logical bit, the portion of the plurality of pointers corresponding to the at least one state value.

18. The method of claim 14, wherein the free list comprises a plurality of bits corresponding to a total number of entry addresses in the common buffer.

19. The method of claim 14, further comprising:

tracking, in a second processing unit, the plurality of triangles to determine if any of the triangles are rejected in the second processing unit;

copying, to the free list, a portion of the plurality of pointers corresponding to triangles rejected in the second processing unit; and

transferring, from the second pointer FIFO to a third pointer FIFO, any of the plurality of pointers corresponding to triangles not rejected in the second processing unit.

20. The method of claim 14, wherein the copying further comprises discarding the portion of the plurality of pointers corresponding to rejected triangles from the first pointer FIFO.

21. The method of claim 14, wherein the copying further comprises writing to a plurality of bits wherein each of the plurality of bits corresponds to a distinct entry address in the common buffer.

22. A method for reducing memory bandwidth usage in a common buffer, multiple first-in-first-out (FIFO) computing environment, comprising:

processing, serially, a plurality of data values in a plurality of pipeline processing units;

storing attribute data, in a common buffer, corresponding to the plurality of data values;

maintaining a plurality of pointers, corresponding to the plurality of data values, in a plurality of FIFO buffers; and

discarding a portion of the plurality of pointers, corresponding to a portion of the plurality of data values that have been rejected by one of the plurality of pipeline processing units.

23. The method of claim 22, further comprising masking a portion of the common buffer, using a free list, to prevent overwriting.

24. The method of claim 23, wherein the masking further comprises updating the free list corresponding to the discarded portion of the plurality of pointers.

25. The method of claim 22, wherein each of the plurality of FIFO pointer buffers is sized to allocate all address entries in the common buffer.

26. The method of claim 22, further comprising:

storing a plurality of index bits in an index field in each of the plurality of pointers; and

storing a plurality of status flag bits in a flag field in each of the plurality of pointers.

27. The method of claim 22, wherein a portion, corresponding to non-rejected portion of the plurality of data values, of the plurality pointers are transferred from one of the plurality of first-in-first-out buffers to a subsequent one of the plurality of first-in-first-out buffers.

28. The method of claim 22, wherein the attribute buffer entry comprises at least one of the following:

attribute delta data and state data.

29. A system for utilizing a common buffer in a multiple first-in-first-out (FIFO) computing environment, comprising:

free list logic configured to maintain availability information regarding a plurality of entry addresses in a common buffer;

FIFO logic configured to store and transfer a plurality of pointer values through a plurality of serially arranged FIFO'"'"'s;

pipeline logic configured to process data utilizing a plurality of serially arranged processing units; and

pointer logic configured to discard any of the plurality of pointers, that correspond to data rejected, from a subsequent one of the plurality of serially arranged FIFO'"'"'s.