NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING REDUCED ELECTRICAL STRESS

• US 20080144378A1
• Filed: 11/29/2007
• Published: 06/19/2008
• Est. Priority Date: 12/14/2006
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Seung-Chul, PARK, Ki-Tae, KIM, Ki-Nam
• Application Number:
  US11/947,007
• Publication Number:
  US 20080144378A1
• Time in Patent Office: Days
• US Class Current: 365/185.05
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A nonvolatile semiconductor memory includes a floating formation switch coupled to a bit line in a memory cell array. The floating formation switch maintains a channel voltage of memory cells coupled to the bit line at a level above a power supply voltage when the bit line is a non-selected bit line, which reduces electrical stress applied to the memory cells connected to the non-selected bit line during a read operation.

Claims

1. A nonvolatile semiconductor memory comprising:

a floating formation switch coupled to a bit line in a memory cell array, the floating formation switch maintaining a channel voltage of memory cells coupled to the bit line at a level above a power supply voltage when the bit line comprises a non-selected bit line, reducing electrical stress applied to the memory cells during a read operation.

2. The memory of claim 1, wherein the bit line corresponds to a cell string of the memory cell array, the cell string comprising the memory cells coupled to the bit line.

3. The memory of claim 1, wherein the level above the power supply voltage is obtained through a self-boosting operation.

4. The memory of claim 2, wherein the floating formation switch comprises a switching transistor coupled between a ground selection transistor and a memory cell positioned farthest from the bit line among the memory cells.

5. The memory of claim 4, wherein the switching transistor comprises a same type of transistor as the memory cells or the ground selection transistor.

6. The memory of claim 2, wherein the floating formation switch comprises first and second switching transistors having channels connected in series between a ground selection transistor and a memory cell positioned farthest from the bit line among the memory cells.

7. The memory of claim 6, wherein each of the first and second switching transistors comprises a same type of transistor as the memory cells or the ground selection transistor.

8. The memory of claim 7, wherein the first and second switching transistors have different threshold voltages.

9. The memory of claim 8, wherein a sequence in which the first and second switching transistors are connected in series to the ground selection transistor is different based on whether the cell string comprises an even cell string or odd cell string.

10. The memory of claim 9, wherein at least one of the first and second switching transistors is turned OFF when the bit line is not selected, and wherein both of the first and second switching transistors are turned ON when the bit line is selected, during the read operation.

11. A nonvolatile semiconductor memory having a memory cell array comprising a plurality of cell strings, each cell string comprising a string selection transistor having a drain connected to a bit line, a ground selection transistor having a source connected to a common source line, and a plurality of memory cell transistors having channels connected in series between a source of the string selection transistor and a drain of the ground selection transistor, the nonvolatile semiconductor memory comprising:

a plurality of floating formation switches corresponding to the plurality of cell strings, each floating formation switch maintaining a channel voltage of each of the plurality of memory cell transistors coupled to a corresponding bit line at a level higher than a power supply voltage when a cell string corresponding to the bit line is not selected, reducing electrical stress on the memory cell transistors of the corresponding cell string when another cell string of the plurality of cell strings in the memory cell array is selected in a read operating mode.

12. The memory of claim 11, wherein reducing the electrical stress reduces a possibility of a read disturbance of the plurality of memory cell transistors.

13. The memory of claim 11, wherein the level higher than the power supply voltage is obtained by performing a self-boosting operation of the plurality of memory cell transistors when the common source line enters a floating state through a switching operation of the floating formation switch.

14. The memory of claim 11, wherein each floating formation switch comprises a switching transistor connected between the ground selection transistor and a memory cell transistor of the plurality of memory cell transistors positioned farthest from the bit line connected to the corresponding cell string.

15. The memory of claim 14, wherein the switching transistor comprises a same type of transistor as the string selection transistor or the memory cell transistors.

16. The memory of claim 11, wherein each floating formation switch comprises first and second switching transistors having channels connected in series between the ground selection transistor and a memory cell transistor of the plurality of memory cell transistors positioned farthest from the bit line connected to the corresponding cell string.

17. The memory of claim 16, wherein a sequence in which the first and second switching transistors are connected to the ground selection transistor differs depending upon whether the corresponding cell string comprises an even cell string or odd cell string.

18. The memory of claim 17, wherein at least one of the first and second switching transistors is turned OFF when the corresponding cell string is not selected, and both of the first and second switching transistors are turned ON when the corresponding cell string is selected, in the read operating mode.

19. A nonvolatile semiconductor memory device, comprising:

a memory cell array comprising a plurality of cell strings, each cell string comprising a first selection transistor having a drain connected to a corresponding bit line, a second selection transistor having a source coupled to a common source line, a plurality of memory cell transistors having channels connected in series to a source of the first selection transistor and which each have a floating gate, and third and fourth selection transistors having channels connected in series to each other between a source of a last memory cell transistor of the plurality of memory cell transistors and a drain of the second selection transistor, the third and fourth selection transistors having different threshold voltage values; and

a read operation controller for controlling one of the third and fourth selection transistors of one of the plurality of cell strings to be turned OFF and a channel voltage of the memory cell transistors of the cell string to be increased to be self-boosted to a level above a power supply voltage when a bit-line corresponding to the cell string is not selected, reducing electrical stress applied to the memory cell transistors belonging to the cell string, when another one of the plurality of cell strings is selected in a read operating mode.

20. The device of claim 19, wherein the third and fourth selection transistors comprise a same type of transistor as the memory cell transistors or the first and second selection transistors.