Memory system, memory device, and output data strobe signal generating method

• US 20080144406A1
• Filed: 02/20/2008
• Published: 06/19/2008
• Est. Priority Date: 10/19/2004
• Status: Active Grant

• Current Assignee: Ho-Young Song, Kwang-Ll Park, Seong-Jin Jang
• Original Assignee: Ho-Young Song, Kwang-Ll Park, Seong-Jin Jang
• Inventors: Song, Ho-Young, Jang, Seong-Jin, Park, Kwang-ll
• Granted Patent: US 7,733,715 B2
• Time in Patent Office: Days
• US Class Current: 365/193
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization

Abstract

An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.

Claims

1-18. -18. (canceled)

19. A semiconductor memory device, comprising:

a command decoder configured to decode a read signal, a dummy read signal, and a mode setting signal;

a mode setting portion configured to set a burst length signal and a CAS latency signal in response to the mode setting signal; and

a preamble cycle calculator configured to generate a preamble cycle signal based on a calculated preamble cycle number.

20. The device of claim 19, wherein the calculated preamble cycle number is calculated by subtracting a cycle number corresponding to the burst length from a cycle number representing a number of cycles occurring between the dummy read signal and the read signal.

21. The device of claim 20, wherein the semiconductor memory device further includes an output data strobe signal generator configured to generate an output data strobe signal in response to the read signal, delay the generated output data strobe signal based on the CAS latency signal and generate a strobe signal of the output data strobe signal.

22. The device of claim 20, wherein the command decoder generates the read signal if a chip selecting signal is activated and a command signal designates a read command and generates the dummy read signal if the chip selecting signal is deactivated and the command signal designates a read command.

23. The device of claim 20, wherein the preamble cycle calculator includes an enable signal generator configured to generate an enable signal which is delayed for a number of cycles based on the burst length, is activated in response to one of the dummy read signal and the read signal and is deactivated in response to a following one of the dummy read signal and the read signal;

a preamble cycle counter configured to perform a counting operation in response to a clock signal if the enable signal is activated and to stop the counting operation to generate the preamble cycle number if the enable signal is deactivated; and

a register configured to store the preamble cycle number and output the preamble cycle signal.

24. The device of claim 20, wherein the mode setting portion is further configured to set a preamble cycle threshold in response to the mode setting signal.

25. The device of claim 24, wherein the preamble cycle counter stops the counting operation if the preamble cycle number becomes the preamble cycle threshold.

26. The device of claim 25, wherein the register initially stores the preamble cycle threshold, stores the calculated preamble cycle number in response to the read signal, and outputs the preamble cycle signal.

27. The device of claim 23, wherein the enable signal generator includes:

a logical sum gate configured to logically sum the dummy read signal and the read signal;

a burst length delay configured to delay an output signal of the logical sum gate for a number of cycles corresponding to the burst length signal; and

a latch configured to generate the enable signal which is activated if an output signal of the burst length delay is activated and deactivated if an output signal of the logical sum gate is activated.

28. The device of claim 27, wherein the burst length delay includes a number of D flip flops which are cascade-connected, and the D flip flops are configured to reset if the output signal of the logical sum gate is activated.

29. The device of claim 24, wherein the preamble cycle counter includes:

a first logical product gate configured to generate the clock signal in response to a comparison signal;

a counter configured to enable if the enable signal is activated, perform the counting operation to generate the calculated preamble cycle number in response to an output signal of the first logical product gate, and reset if the enable signal is deactivated; and

a comparator configured to compare the calculated preamble cycle number with the preamble cycle threshold and generate the comparison signal.

30. The device of claim 29, wherein the counter includes a number of flip flops which are cascade-connected and configured to perform the counting operation in response to the output signal of the first logical product gate.

31. The device of claim 30, wherein each of the cascade-connected flip flops includes:

a second logical product gate configured to AND an input signal and a counting output signal to generate an output signal;

an XOR gate configured to XOR the input signal and a counting input signal; and

a D flip flop configured to latch an output signal of the XOR gate to generate as the counting output signal in response to the clock signal,

wherein the enable signal is applied to a first one of the cascade-connected flip flops as the input signal, a ground voltage is applied as a counting input signal of the first one of the cascade-connected flip flops, and an output signal and a counting output signal of a prior cascade-connected flip flop are applied as an input signal and a counting input signal of a following cascade-connected flip flop.

32-39. -39. (canceled)

40. An output data strobe signal generating method comprising:

generating a read signal, a dummy read signal, and a mode setting signal in response to a command signal and a chip selecting signal;

setting a burst length signal, a CAS latency signal and a preamble cycle signal in response to the mode setting signal;

calculating a preamble cycle number; and

generating a preamble cycle signal based on the calculated preamble cycle number.

41. The method of claim 40, wherein calculating the preamble cycle number includes subtracting a cycle number corresponding to the burst length from a cycle number representing a number of cycles occurring between the dummy read signal and the read signal.

42. The method of claim 41, further comprising:

generating an output data strobe signal in response to the read signal;

delaying the generated output data strobe signal for a number of cycles corresponding to the CAS latency signal;

and generating a strobe signal of the output data strobe signal.

43. The method of claim 41, wherein generating the read signal, the dummy signal, and the mode setting signal includes generating the read signal if the chip selecting signal is activated and the command signal designates a read command, and generating the dummy read signal if the chip selecting signal is deactivated and the command signal designates a read command.

44. The method of claim 43, wherein generating the preamble signal based on the calculated preamble cycle number includes:

generating an enable signal which is delayed for a number of cycles corresponding to the burst length signal, activated in response to one of the dummy read signal and the read signal, and deactivated in response to a following one of the dummy read signal and the read signal;

performing a counting operation in response to a clock signal if the enable signal is activated;

stopping the counting operation if the calculated preamble cycle number becomes the preamble cycle threshold; and

storing the preamble cycle signal threshold and the calculated preamble cycle number; and

generating the preamble cycle signal.