Memory system, memory device, and output data strobe signal generating method
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Abstract
An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.
6 Citations
44 Claims
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1-18. -18. (canceled)
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19. A semiconductor memory device, comprising:
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a command decoder configured to decode a read signal, a dummy read signal, and a mode setting signal; a mode setting portion configured to set a burst length signal and a CAS latency signal in response to the mode setting signal; and a preamble cycle calculator configured to generate a preamble cycle signal based on a calculated preamble cycle number. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32-39. -39. (canceled)
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40. An output data strobe signal generating method comprising:
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generating a read signal, a dummy read signal, and a mode setting signal in response to a command signal and a chip selecting signal; setting a burst length signal, a CAS latency signal and a preamble cycle signal in response to the mode setting signal; calculating a preamble cycle number; and generating a preamble cycle signal based on the calculated preamble cycle number. - View Dependent Claims (41, 42, 43, 44)
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Specification