Semiconductor memory, operating method of semiconductor memory, memory controller, and system

• US 20080144417A1
• Filed: 11/30/2007
• Published: 06/19/2008
• Est. Priority Date: 12/15/2006
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Memory Solution Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Fujioka, Shinya, Okuyama, Yoshiaki, Eguchi, Yasuyuki
• Granted Patent: US 7,746,718 B2
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A refresh register stores disable block information indicating a memory block whose refresh operation is to be disabled. A refresh control circuit periodically executes the refresh operation of a memory block except the memory block corresponding to the disable block information. During an access cycle to one of the memory blocks, the register control circuit writes the disable block information to the refresh register according to an external input. Consequently, in order to rewrite the refresh register, it is not necessary to use an additional operation cycle to the access cycle. Since there is no need to insert an extra operation cycle, it is possible to change a memory area to be refreshed without lowering effective efficiency of access cycles. As a result, power consumption can be reduced.

Claims

1. A semiconductor memory comprising:

a plurality of memory blocks each having dynamic memory cells;

a refresh register storing disable block information indicating a memory block whose refresh operation is to be disabled;

a refresh control circuit periodically executing the refresh operation of a memory block except the memory block corresponding to the disable block information stored in the refresh register; and

a register control circuit writing the disable block information to the refresh register according to an external input, during an access cycle to one of the memory blocks.

2. The semiconductor memory according to claim 1, further comprising

a data terminal receiving a data signal to be written to the memory cell or outputting a data signal read from the memory cell, wherein

the register control circuit writes to the refresh register the block disable information supplied via the data terminal during a period in which the data signal is not transmitted to the data terminal.

3. The semiconductor memory according to claim 2, further comprising

a command terminal receiving a register command signal to rewrite the refresh register, wherein

the register control circuit writes to the refresh register the block disable information supplied via the data terminal in synchronization with the register command signal.

4. The semiconductor memory according to claim 2, further comprising

a dedicated terminal receiving a dedicated signal to write the refresh register, wherein

the register control circuit writes to the refresh register the block disable information supplied via the data terminal in synchronization with the dedicated signal.

5. The semiconductor memory according to claim 2, wherein:

the semiconductor memory receives an access command signal to execute the access cycle, in synchronization with a first edge of a clock signal, and receiving write data at and outputting read data from the data terminal in synchronization with a second edge of the clock signal, the second edge appearing later than the first edge, and

the register control circuit writes to the refresh register the block disable information supplied via the data terminal in synchronization with a middle edge existing between the first edge and the second edge or in synchronization with the first edge.

6. The semiconductor memory according to claim 2, further comprising:

an address/data terminal receiving an address signal indicating a memory cell to be accessed, and receiving a data signal to be written to the memory cell or outputting a data signal read from the memory cell, wherein

the register control circuit writes to the refresh register the block disable information supplied via the address/data terminal during a period in which neither the address signal nor the data signal is transmitted to the address/data terminal.

7. The semiconductor memory according to claim 1, further comprising

an address terminal receiving an address signal indicating a memory cell to be accessed, wherein

the register control circuit writes to the refresh register the block disable information supplied via the address terminal during a period in which the address signal is not supplied via the address terminal.

8. The semiconductor memory according to claim 7, further comprising

a command terminal receiving a register command signal to rewrite the refresh register, wherein

the register control circuit writes to the refresh register the block disable information supplied via the address terminal in synchronization with the register command signal.

9. The semiconductor memory according to claim 7, further comprising

a dedicated terminal receiving a dedicated signal to rewrite the refresh register, wherein

the register control circuit writes to the refresh register the block disable signal supplied via the address terminal in synchronization with the dedicated signal.

10. The semiconductor memory according to claim 7, wherein:

the semiconductor memory receives the address signal and an access command signal to execute the access cycle, in synchronization with a first edge of a clock signal, and

the register control circuit writes to the refresh register the block disable information supplied via the address terminal in synchronization with a second edge of the clock signal, the second edge appearing later than the first edge.

11. The semiconductor memory according to claim 1, further comprising:

a data terminal receiving a data signal to be written to the memory cell or outputting a data signal read from the memory cell; and

an address terminal receiving an address signal indicating the memory cell to be accessed, wherein;

the register control circuit outputs an area set signal in response to an access command signal to access the memory cell; and

the refresh register stores, in synchronization with the area set signal, the block disable information supplied via at least one of the data terminal and the address terminal.

12. The semiconductor memory according to claim 11, further comprising

a clock delay circuit delaying the access command signal by a predetermined number of clock cycles, wherein

the register control circuit outputs the area set signal in synchronization with the access command signal delayed by the clock delay circuit.

13. An operating method of a semiconductor memory having a plurality of memory blocks each having dynamic memory cells, the method comprising:

writing the disable block information, indicating a memory block whose refresh operation is to be disabled, to the refresh register according to an external input, during an access cycle to one of the memory blocks; and

periodically executing the refresh operation of a memory block except the memory block corresponding to the disable block information stored in the refresh register.

14. The operating method of the semiconductor memory according to claim 13, further comprising

receiving a data signal to be written to the memory cell at a data terminal or outputting, from the data terminal, a data signal read from the memory cell, wherein

the block disable information supplied via the data terminal during a period in which the data signal is not transmitted via the data terminal is written to the refresh register.

15. The operating method of the semiconductor memory according to claim 13, further comprising

receiving, at an address terminal, an address signal indicating a memory cell to be accessed, wherein

the block disable information supplied via the address terminal during a period in which the address signal is not supplied via the address terminal is written to the refresh register.

16. A memory controller controlling an operation of a semiconductor memory, wherein the memory controller outputs a disable block information via one of a data terminal, and an address terminal of the semiconductor memory during a period in which a data signal is not input/output to/from the semiconductor memory or during a period in which an address signal is not output to the semiconductor memory in an access cycle in which the memory controller accesses the semiconductor memory.

17. The memory controller according to claim 16, comprising:

a refresh area control unit generating the disable block information according to a memory area that at least one master controller uses in the semiconductor memory, the master controller accessing the semiconductor memory via the memory controller; and

a timing control unit which outputs to the semiconductor memory a command signal, the address signal, and a data signal received from the master controller in order to access the semiconductor memory, and which outputs to the semiconductor memory the disable block information generated by the refresh area control unit, during a period in which the disable block information does not compete with one of the address signal and the data signal output from the master controller.

18. The memory controller according to claim 17, wherein

the refresh area control unit comprises an area conversion unit which, according to a use area signal indicating the memory area that the master controller uses in the semiconductor memory, generates the disable block information indicating a memory block except a memory block including the memory area indicated by the use area signal.

19. The memory controller according to claim 18, wherein

the refresh area control unit comprises an external memory area register which stores the memory area that each of the master controllers uses in the semiconductor memory and which receives a master selection signal indicating that the master controller uses the semiconductor memory and outputs, as the use area signal, the memory area corresponding to the received master selection signal.

20. A system having a semiconductor memory, a memory controller controlling access to the semiconductor memory and at least one master controller accessing the semiconductor memory via the memory controller, wherein

the semiconductor memory comprises:

a plurality of memory blocks each having dynamic memory cells;

a refresh register storing disable block information indicating a memory block whose refresh operation is to be disabled;

a refresh control circuit periodically executing the refresh operation of a memory block except the memory block corresponding to the disable block information stored in the refresh register; and

a register control circuit writing the disable block information to the refresh register according to an external input, during an access cycle to one of the memory blocks; and

the memory controller outputs the disable block information to a data terminal or an address terminal of the semiconductor memory, during a period in which a data signal is not input/output to/from the semiconductor memory or during a period in which an address signal is not output to the semiconductor memory in an access cycle to the semiconductor memory accompanying an access request from the master controller.