Time division duplex forward-to-reverse transition signal generator

• US 20080144543A1
• Filed: 12/11/2007
• Published: 06/19/2008
• Est. Priority Date: 12/13/2006
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hunton, Matthew J., Carichner, Scott
• Application Number:
  US12/001,397
• Publication Number:
  US 20080144543A1
• Time in Patent Office: Days
• US Class Current: 370/280
• CPC Class Codes: H04B 1/18 Input circuits, e.g. for coupling to an antenna or a transmission line coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

A transition signal generator is used to for controlling a booster of a time division duplex signal in a communications system. The transition signal generator includes a signal sampler for sampling the time division duplex signal, a power detector for detecting a power of the sampled signal, and a timing control unit for generating a logic signal indicating a direction of the sampled signal from the detected power of the sampled signal.

Claims

1. A transition signal generator, comprising:

a signal sampler for sampling a time division duplex signal from a signal path in a communications system;

a power detector for detecting a power of the sampled signal; and

a timing control unit for generating a logic signal indicating a direction of the sampled signal from the detected power of the sampled signal.

2. A transition signal generator as set out in claim 1, wherein the signal sampler comprises a directional coupler.

3. A transition signal generator as set out in claim 1, wherein the timing control unit generates the logic signal based on the rising or falling edge of the detected power of the sampled signal.

4. A transition signal generator as set out in claim 3, wherein the logic signal is offset in time from the edge of the detected power of the sampled signal.

5. A transition signal generator as set out in claim 4, wherein the logic signal is offset by one or more periods less a detection delay.

6. A transition signal generator as set out in claim 5, wherein the logic signal is offset by one period less the detection delay.

7. A transition signal generator as set out in claim 3, wherein the timing control unit further generates the logic signal based on the width between rising and falling edges of the sampled signal.

8. The transition signal generator as set out in claim 7, wherein the width of the logic signal is greater than the width of the sampled signal.

9. The transition signal generator as set out in claim 1, wherein the sampled signal from the signal path has a forward signal power substantially higher than a reverse signal power.

10. A wireless communication system, comprising:

a base station;

an antenna for outputting a forward signal from, or feeding a reverse signal to, the base station on a time division duplex basis;

a booster coupled between the base station and the antenna for boosting at least one of the forward and the reverse signal; and

a transition signal generator coupled to the base station and the booster to sample a time division duplex signal between the base station and the antenna and to control the booster, the transition signal generator comprising a signal sampler for sampling the time division duplex signal between the base station and the antenna, and means for generating a logic signal indicating a direction of the sampled signal to control the booster.

11. A wireless communication system as set out in claim 10, wherein the booster selectively boosts the forward signal or the reverse signal based on the logic signal generated by the transition signal generator.

12. A wireless communication system as set out in claim 10, wherein the time division duplex signal includes a forward signal, a reverse signal, and a reverse to forward gap between the forward signal and the reverse signal, and wherein the forward signal has substantially higher power than the reverse signal.

13. A wireless communication system as set out in claim 10, wherein the signal sampler comprises a directional coupler.

14. A wireless communication system as set out in claim 12, wherein the transition signal generator further comprises a power detector for detecting a power of the sampled signal.

15. A wireless communication system as set out in claim 14, wherein the power detector is a logarithmic power detector.

16. A wireless communication system as set out in claim 14, wherein the transition signal generator determines whether the signal is forward or reverse based on the detected power of the sampled signal.

17. A method for controlling a booster of a time division duplex signal between a base station and an antenna, comprising:

sampling the time division duplex signal;

determining a signal direction as being forward or reverse based on the sampled signal; and

controlling the booster based on the determined signal direction.

18. A method as set out in claim 17, wherein the time division duplex signal includes a forward signal, a reverse signal, and a reverse to forward gap between the forward signal and the reverse signal, and wherein the forward signal has a substantially higher power than the reverse signal.

19. A method as set out in claim 18, further comprising:

detecting a power of the sampled signal,

wherein determining the signal direction is based on the detected power of the sampled signal.

20. A method as set out in claim 19, further comprising:

outputting a logic signal indicating the signal direction,

wherein the logic signal timing is based on the detected power of the sampled signal.

21. A method as set out in claim 20, further comprising adjusting the logic signal timing to compensate for a delay of the sampled signal relative to the time division duplex signal.

22. A method as set out in claim 21, wherein the logic signal is offset in time from the detected power of the sampled signal.

23. A method as set out in claim 22, wherein the logic signal is offset by one or more periods less a detection delay.

24. A method as set out in claim 23, wherein the logic signal is offset by one period less the detection delay.

25. A method as set out in claim 20, wherein the logic signal is based on the width and a rising edge period of the detected power of the sampled signal.