SEMICONDUCTOR PROCESSING SYSTEM WITH ULTRA LOW-K DIELECTRIC

• US 20080145795A1
• Filed: 12/19/2006
• Published: 06/19/2008
• Est. Priority Date: 12/19/2006
• Status: Active Grant

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Inventors: Widodo, Johnny, Hsia, Liang-Choo, Zhang, Bei Chao, Yudhistira, Yasri
• Granted Patent: US 7,622,403 B2
• Time in Patent Office: Days
• US Class Current: 430/313
• CPC Class Codes: G03F 7/0035 Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31133 by chemical means
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 2221/1047 the air gaps being formed by pores in the dielectric

Abstract

A semiconductor processing system with ultra low-K dielectric is provided including providing a substrate having an electronic circuit, forming an ultra low-K dielectric layer, having porogens, over the substrate, blocking an incoming radiation from a first region of the ultra low-K dielectric layer, evaporating the porogens from a second region of the ultra low-K dielectric layer by projecting the incoming radiation on the second region, and removing the ultra low-K dielectric layer in the first region with a developer.

Claims

1. A semiconductor processing system with ultra low-K dielectric comprising:

providing a substrate having an electronic circuit;

forming an ultra low-K dielectric layer, having porogens, over the substrate;

blocking an incoming radiation from a first region of the ultra low-K dielectric layer;

evaporating the porogens from a second region of the ultra low-K dielectric layer by projecting the incoming radiation on the second region; and

removing the ultra low-K dielectric layer in the first region with a developer.

2. The system as claimed in claim 1 further comprising forming a channel in the ultra low-K dielectric layer by removing the ultra low-K dielectric layer in the first region.

3. The system as claimed in claim 1 further comprising providing a reticle for projecting a pattern on a photoresist layer.

4. The system as claimed in claim 1 further comprising forming a nanopore includes projecting an ultraviolet light on a matrix of the porogens.

5. The system as claimed in claim 1 wherein removing the porogens includes using a developer to etch a path for a conductive material.

6. A semiconductor processing system with ultra low-K dielectric comprising:

providing a substrate having an electronic circuit;

forming an ultra low-K dielectric layer, having porogens, over the substrate including forming an insulator on a conductive material;

blocking an incoming radiation from a first region of the ultra low-K dielectric layer including blocking the incoming radiation using a photoresist mask or a reticle;

evaporating the porogens from a second region of the ultra low-K dielectric layer by projecting the incoming radiation on the second region to form a nanopore; and

removing the porogens from the ultra low-K dielectric layer includes selectively removing the first region from the ultra low-K dielectric layer with a developer.

7. The system as claimed in claim 6 further comprising forming a channel in the ultra low-K dielectric layer for depositing the conductive material.

8. The system as claimed in claim 6 further comprising providing a reticle for projecting a pattern on a photoresist layer includes providing a translucent section and an opaque section.

9. The system as claimed in claim 6 wherein forming the nanopore includes:

illuminating a matrix of the porogens with an ultraviolet light including chemically altering the ultra low-K dielectric layer; and

evaporating the porogens to evacuate the nanopores.

10. The system as claimed in claim 6 wherein removing the porogens includes using the developer for removing the photoresist mask and the porogens in the first region including forming a path for the conductive material.

11. A semiconductor processing system with ultra low-K dielectric comprising:

a substrate having an electronic circuit;

an ultra low-K dielectric layer, having porogens, over the substrate;

a first region of the ultra low-K dielectric layer having an incoming radiation blocked;

the porogens evaporated from a second region of the ultra low-K dielectric layer by the incoming radiation projected on the second region; and

the ultra low-K dielectric layer removed in the first region with a developer.

12. The system as claimed in claim 11 further comprising a channel formed in the ultra low-K dielectric layer includes the porogens removed.

13. The system as claimed in claim 11 further comprising a reticle for a pattern projected on the photoresist layer.

14. The system as claimed in claim 11 further comprising a nanopore formed includes a matrix of the porogens illuminated by an ultraviolet light.

15. The system as claimed in claim 11 further comprises a conductive material deposited in the channel formed in the ultra low-K dielectric layer.

16. The system as claimed in claim 11 further comprising:

an insulator formed on a conductive material; and

a first region of the ultra low-K dielectric layer selectively removed with a developer.

17. The system as claimed in claim 16 further comprises a channel formed in the ultra low-K dielectric layer for depositing the conductive material.

18. The system as claimed in claim 16 further comprising a reticle for a pattern projected on a photoresist layer.

19. The system as claimed in claim 16 further comprising a nanopore formed includes:

a matrix of the porogens illuminated by an ultraviolet light includes the ultra low-K dielectric layer chemically altered; and

the porogens evaporated to evacuate the nanopores.

20. The system as claimed in claim 16 wherein the porogens removed includes the photoresist mask and the porogens in the first region removed by the developer includes a path for the conductive material formed.