EMBEDDED SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
First Claim
1. A method for fabricating an embedded semiconductor memory device, comprising:
- preparing a semiconductor substrate comprising region IA and region IB;
forming gate dielectric layers and gate structures sequentially on the semiconductor substrate, with the gate dielectric layers in region IA being a charge trap region, and the gate dielectric layers in region IB being a non-charge trap region;
forming source/drain extension regions in region IA and region IB; and
forming source/drain regions in region IA and region IB, wherein upon application of a voltage to the gate structures, the respective source/drain regions are electrically connected through channels formed in the semiconductor substrate.
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Abstract
The invention discloses a method for fabricating an embedded semiconductor memory device, comprising: preparing a semiconductor substrate comprising a region IA and a region IB; forming gate dielectric layers and gate structures sequentially on the semiconductor substrate, with the gate dielectric layer in region IA being a charge trap region, and the gate dielectric layer in region IB being a non-charge trap region; forming source/drain extension regions in region IA and region IB of the semiconductor substrate; and forming source/drain regions in region IA and region IB of the semiconductor substrate. There is provided correspondingly an embedded semiconductor memory device. The invention also provides an embedded semiconductor memory device and a method for fabricating the same. A two-bit storage operation can be enabled for the embedded semiconductor memory device according to the invention so as to achieve high-density storage. Furthermore, the process for forming a logic circuit can be compatible with that for forming a memory device circuit according to the invention.
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Citations
24 Claims
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1. A method for fabricating an embedded semiconductor memory device, comprising:
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preparing a semiconductor substrate comprising region IA and region IB; forming gate dielectric layers and gate structures sequentially on the semiconductor substrate, with the gate dielectric layers in region IA being a charge trap region, and the gate dielectric layers in region IB being a non-charge trap region; forming source/drain extension regions in region IA and region IB; and forming source/drain regions in region IA and region IB, wherein upon application of a voltage to the gate structures, the respective source/drain regions are electrically connected through channels formed in the semiconductor substrate. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An embedded semiconductor memory device, comprising:
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a semiconductor substrate comprising region IA and region IB; gate dielectric layers and gate structures formed sequentially on the semiconductor substrate; source/drain extension regions formed in region IA and region IB; and source/drain regions formed in region IA and region IB, wherein upon application of a voltage to the gate structures, the respective source/drain regions are electrically connected through conductive channels formed in the semiconductor substrate; wherein the gate dielectric layer in region IA is a charge trap region, and the gate dielectric layer in region IB is a non-charge trap region. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A method for fabricating an embedded semiconductor memory device, comprising:
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preparing a semiconductor substrate comprising region I and region II, said region I being a core circuit region and including region i and region ii, said region II being an IO (Input and Output) circuit region and comprising region iii and region iv; forming gate dielectric layers and gate structures sequentially in region I and region II of the semiconductor substrate, with the gate dielectric layers in region i and/or region iii being a charge trap region, and the gate dielectric layers in region ii and/or region iv being a non-charge trap region; forming source/drain extension regions in region I and region II; and forming source/drain regions in region I and region II respectively, wherein upon application of a voltage to the gate structures, the respective source/drain regions are electrically connected through conductive channels formed in the semiconductor substrate. - View Dependent Claims (14, 15, 16, 17, 18)
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19. An embedded semiconductor memory device, comprising:
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a semiconductor substrate comprising region I and region II, said region I being a core circuit region and including region i and region ii, said region II being an IO (Input and Output) circuit region and including region iii and region iv; the gate dielectric layers and the gate structures formed sequentially on the semiconductor substrate; the source/drain extension regions formed respectively in region I and region II; and the source/drain regions formed respectively in region I and region II, wherein upon application of a voltage to the gate structures, the respective source/drain regions are connected electrically through conductive channels formed in the semiconductor substrate, wherein the gate dielectric layer in region i and/or region iii is a charge trap region, and the gate dielectric layer in region ii and/or region iv is a non-charge trap region. - View Dependent Claims (20, 21, 22, 23, 24)
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Specification