EMBEDDED SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME

• US 20080145985A1
• Filed: 10/11/2007
• Published: 06/19/2008
• Est. Priority Date: 12/15/2006
• Status: Abandoned Application

• Current Assignee: Semiconductor Manufacturing International (Beijing) Corporation (Semiconductor Manufacturing International Corporation)
• Original Assignee: Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: CHI, Min-hwa
• Application Number:
  US11/871,127
• Publication Number:
  US 20080145985A1
• Time in Patent Office: Days
• US Class Current: 438/199
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

The invention discloses a method for fabricating an embedded semiconductor memory device, comprising: preparing a semiconductor substrate comprising a region IA and a region IB; forming gate dielectric layers and gate structures sequentially on the semiconductor substrate, with the gate dielectric layer in region IA being a charge trap region, and the gate dielectric layer in region IB being a non-charge trap region; forming source/drain extension regions in region IA and region IB of the semiconductor substrate; and forming source/drain regions in region IA and region IB of the semiconductor substrate. There is provided correspondingly an embedded semiconductor memory device. The invention also provides an embedded semiconductor memory device and a method for fabricating the same. A two-bit storage operation can be enabled for the embedded semiconductor memory device according to the invention so as to achieve high-density storage. Furthermore, the process for forming a logic circuit can be compatible with that for forming a memory device circuit according to the invention.

Claims

1. A method for fabricating an embedded semiconductor memory device, comprising:

preparing a semiconductor substrate comprising region IA and region IB;

forming gate dielectric layers and gate structures sequentially on the semiconductor substrate, with the gate dielectric layers in region IA being a charge trap region, and the gate dielectric layers in region IB being a non-charge trap region;

forming source/drain extension regions in region IA and region IB; and

forming source/drain regions in region IA and region IB, wherein upon application of a voltage to the gate structures, the respective source/drain regions are electrically connected through channels formed in the semiconductor substrate.

2. The method for fabricating an embedded semiconductor memory device according to claim 1, wherein the formation of the gate dielectric layers further comprises:

forming a high-k dielectric layer on the semiconductor substrate as the gate dielectric layer, such as HfO₂, Al₂O₃, La₂O₃, HfSiON or HfAlO₂, with charge traps therein; and

performing an ion implantation in the gate dielectric layer in region IB to eliminate the charge traps, thus forming a non-charge trap region in the gate dielectric layer in region IB and a charge trap region in the gate dielectric layer in region IA.

3. The method for fabricating an embedded semiconductor memory device according to claim 2, wherein the implanted ions are fluorine ions or nitrogen ions, the implantation energy is determined in accordance with thickness of the gate structures and the gate dielectric layers, and the implantation dosage ranges from 1.0E+11 to 1.0E+15 cm⁻

2.

4. The method for fabricating an embedded semiconductor memory device according to claim 1, wherein the formation of the gate dielectric layers further comprises:

forming the gate dielectric layers on the semiconductor substrate, said gate dielectric layers comprising silicon oxide, silicon nitride or a combination thereof, performing an ion implantation in the gate dielectric layer in region IA to generate charge traps, thus forming a charge trap region in the gate dielectric layer in region IA and a non-charge trap region in the gate dielectric layer in region IB.

5. The method for fabricating an embedded semiconductor memory device according to claim 4, wherein the implanted ions are silicon ions, germanium, nitrogen or hafnium ions, the implantation dosage ranges from 1.0E+11 to 1.0E+13 cm⁻

2, the implantation energy is determined in accordance with the implanted ions and thickness of the gate structures, and the implantation angle ranges from 0°

to 60°

.

6. The method for fabricating an embedded semiconductor memory device according to claim 1, wherein the channel of the embedded semiconductor memory device is an n-type or a p-type, the ions implanted into the source/drain extension region of the n-type channel embedded semiconductor memory device are arsenic or antimony or phosphorous ions, and the ions implanted into the source/drain extension region of the p-type channel embedded semiconductor memory device are indium or boron ions.

7. An embedded semiconductor memory device, comprising:

a semiconductor substrate comprising region IA and region IB;

gate dielectric layers and gate structures formed sequentially on the semiconductor substrate;

source/drain extension regions formed in region IA and region IB; and

source/drain regions formed in region IA and region IB, wherein upon application of a voltage to the gate structures, the respective source/drain regions are electrically connected through conductive channels formed in the semiconductor substrate;

wherein the gate dielectric layer in region IA is a charge trap region, and the gate dielectric layer in region IB is a non-charge trap region.

8. The embedded semiconductor memory device according to claim 7, wherein the gate dielectric layers are high-k dielectric material, such as HfO₂, Al₂O₃, La₂O₃, HfSiON or HfAlO₂, with charge traps therein, the gate dielectric layer in region IB forms a non-charge trap region by an ion implantation to eliminate the charge traps, and the gate dielectric layer in region IA forms a charge trap region.

9. The embedded semiconductor memory device according to claim 8, wherein the implanted ions are fluorine ions or nitrogen ions, the implantation energy is determined in accordance with thickness of the gate structures and the gate dielectric layers, and the implantation dosage ranges from 1.0E+11 to 1.0E+15 cm⁻

2.

10. The embedded semiconductor memory device according to claim 7, wherein the gate dielectric layers comprise silicon oxide, silicon nitride or a combination thereof, the gate dielectric layers in region IA forms a charge trap region by an ion implantation, and the gate dielectric layer in region IB forms a non-charge trap region.

11. The embedded semiconductor memory device according to claim 10, wherein the implanted ions are silicon ions, germanium ions, nitrogen ions or hafnium ions, the implantation dosage ranges from 1.0E+11 to 1.0E+13 cm⁻

2, the implantation energy is determined in accordance with the implanted ions and thickness of the gate structures, and the implantation angle ranges from 0°

to 60°

.

12. The embedded semiconductor memory device according to claim 7, wherein the channel of an embedded semiconductor memory device is an n-type or a p-type, the ions implanted into the source/drain extension regions of the n-type channel embedded semiconductor memory device are arsenic ions or antimony ions or phosphorous ions, and the ions implanted into the source/drain extension regions of the p-type channel embedded semiconductor memory device are indium ions or boron ions.

13. A method for fabricating an embedded semiconductor memory device, comprising:

preparing a semiconductor substrate comprising region I and region II, said region I being a core circuit region and including region i and region ii, said region II being an IO (Input and Output) circuit region and comprising region iii and region iv;

forming gate dielectric layers and gate structures sequentially in region I and region II of the semiconductor substrate, with the gate dielectric layers in region i and/or region iii being a charge trap region, and the gate dielectric layers in region ii and/or region iv being a non-charge trap region;

forming source/drain extension regions in region I and region II; and

forming source/drain regions in region I and region II respectively, wherein upon application of a voltage to the gate structures, the respective source/drain regions are electrically connected through conductive channels formed in the semiconductor substrate.

14. The method for fabricating an embedded semiconductor memory device according to claim 13, wherein the formation of the gate dielectric layers may further comprises:

forming a high-k dielectric layer on the semiconductor substrate as the gate dielectric layers, such as HfO₂, Al₂O₃, La₂O₃, HfSiON or HfAlO₂, with charge traps therein; and

performing a first ion implantation and/or a second ion implantation in the gate dielectric layer in region ii and/or region iv to eliminate the charge traps, thus forming a non-charge trap region in region ii and/or region iv and a charge trap region in the gate dielectric layer in region i and/or region iii.

15. The method for fabricating an embedded semiconductor memory device according to claim 14, wherein the ions for the first ion implantation and/or the second ion implantation are fluorine ions or nitrogen ions, the implantation energy for the first ion implantation and/or the second ion implantation is determined in accordance with the implanted ions and thickness of the gate structures, and the implantation dosage for the first ion implantation and/or the second ion implantation ranges from 1.0E+11 to 1.0E+15 cm⁻

2.

16. The method for fabricating an embedded semiconductor memory device according to claim 13, wherein the formation of the gate dielectric layers further comprises:

forming the gate dielectric layers on the semiconductor substrate, said gate dielectric layers comprising silicon oxide, silicon nitride or a combination thereof, and performing a first ion implantation and/or a second ion implantation in the gate dielectric layer in region i and/or region iii to generate charge traps, thus forming a charge trap region in region i and/or region iii and a non-charge trap region in region ii and/or region iv.

17. The method for fabricating an embedded semiconductor memory device according to claim 16, wherein the ions for the first ion implantation and/or the second ion implantation are silicon ions, germanium ions, nitrogen ions or hafnium ions, the implantation dosage for the first ion implantation and/or the second ion implantation ranges from 1.0E+11 to 1.0E+13 cm⁻

2, the implantation energy for the first ion implantation and/or the second ion implantation is determined in accordance with the implanted ions and thickness of the gate structures, and the implantation angle for the first ion implantation and/or the second ion implantation ranges from 0°

to 60°

.

18. The method for fabricating an embedded semiconductor memory device according to claim 13, wherein the channel of an embedded semiconductor memory device is an n-type or a p-type, the ions implanted into the source/drain extension region of the n-type channel embedded semiconductor memory device are arsenic ions or antimony ions or phosphorous ions, and the ions implanted into the source/drain extension region of the p-type channel embedded semiconductor memory device are indium ions or boron ions.

19. An embedded semiconductor memory device, comprising:

a semiconductor substrate comprising region I and region II, said region I being a core circuit region and including region i and region ii, said region II being an IO (Input and Output) circuit region and including region iii and region iv;

the gate dielectric layers and the gate structures formed sequentially on the semiconductor substrate;

the source/drain extension regions formed respectively in region I and region II; and

the source/drain regions formed respectively in region I and region II, wherein upon application of a voltage to the gate structures, the respective source/drain regions are connected electrically through conductive channels formed in the semiconductor substrate, wherein the gate dielectric layer in region i and/or region iii is a charge trap region, and the gate dielectric layer in region ii and/or region iv is a non-charge trap region.

20. The embedded semiconductor memory device according to claim 19, wherein the gate dielectric layers are high-k dielectric materials, such as HfO₂, Al₂O₃, La₂O₃, HfSiON or HfAlO₂, with charge traps therein, the gate dielectric layer in region ii and/or region iv forms a non-charge trap region by a first ion implantation and/or a second ion implantation to eliminate the charge traps, and the gate dielectric layer in region i and/or region iii forms a charge trap region.

21. The embedded semiconductor memory device according to claim 20, wherein the ions for the first ion implantation and/or the second ion implantation are fluorine ions or nitrogen ions, the implantation energy for the first ion implantation and/or the second ion implantation is determined in accordance with the implanted ions and thickness of the gate structures, and the implantation dosage for the first ion implantation and/or the second ion implantation ranges from 1.0E+11 to 1.0E+15 cm⁻

2.

22. The embedded semiconductor memory device according to claim 19, wherein the gate dielectric layers comprising silicon oxide, silicon nitride or a combination thereof, the gate dielectric layers in region i and/or region iii forms a charge trap region by a first ion implantation and/or a second ion implantation to eliminate the charge traps, and the gate dielectric layers in region ii and/or region iv forms a non-charge trap region.

23. The embedded semiconductor memory device according to claim 22, wherein ions for the first ion implantation and/or the second ion implantation are silicon ions, germanium ions, nitrogen ions or hafnium ions, the implantation dosage for the first ion implantation and/or the second ion implantation ranges from 1.0E+11 to 1.0E+13 cm⁻

2, the implantation energy for the first ion implantation and/or the second ion implantation is determined in accordance with the implanted ions and thickness of the gate structures, and the implantation for the first ion implantation and/or the second ion implantation ranges from 0°

to 60°

.

24. The embedded semiconductor memory device according to claim 19, wherein the channel of an embedded semiconductor memory device is an n-type or a p-type, the ions implanted into the source/drain extension region of the n-type channel embedded semiconductor memory device are arsenic ions or antimony ions or phosphorous ions, and the ions implanted into the source/drain extension region of the p-type channel embedded semiconductor memory device are indium ions or boron ions.