Die and Wafer Failure Classification System and Method

• US 20080147355A1
• Filed: 12/19/2006
• Published: 06/19/2008
• Est. Priority Date: 12/19/2006
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda North America Corporation (Infineon Technologies AG)
• Inventors: Fields, Kevin L., Bynum, Timothy J.A.
• Granted Patent: US 7,415,387 B2
• Time in Patent Office: Days
• US Class Current: 702/183
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851

Abstract

A system and method for classifying failures of semiconductor integrated circuit dies using a unique input vector created from die level characterization data to classify wafer (process related) and die level (defect related) patterns. The failure classification may then be used to assign the appropriate yield loss by die. The classification results produced by the plurality of classifiers are examined with a preference towards assigning a wafer level failure classification to failure data for a die when any of the plurality of failure classification results indicates a presence of a wafer level failure.

Claims

1. A method for classifying failures of integrated circuit dies, comprising:

analyzing failure data for each of a plurality of dies on a wafer with a plurality of failure classifiers to produce a corresponding plurality of failure classification results for each die, wherein the failure data for each die combines bin map failure data, electrical analysis data and physical failure data for the die; and

for the failure data for each die, analyzing the plurality of failure classification results to assign a particular one of a plurality of failure classifications to each die, wherein analyzing comprises analyzing the plurality of failure classification results with a preference towards assigning a wafer level failure classification to failure data for a die when any of the plurality of failure classification results indicates a presence of a wafer level failure.

4. The method of claim 1, and further comprising counting the number of die assigned to each of the plurality of failure classifications.

6. The method of claim 1, wherein analyzing comprises analyzing the failure data for each die with at least one die level classifier to produce a die level classification result and with at least one wafer level classifier to produce a wafer level classification result.

2. (canceled)

3. (canceled)

5. A method for classifying failures of integrated circuit dies, comprising:

analyzing failure data for each of a plurality of dies on a wafer with a plurality of failure classifiers to produce a corresponding plurality of failure classification results for each die, wherein the failure data for each die combines bin map failure data, electrical analysis data and physical failure data for the die; and

for the failure data for each die, analyzing the plurality of failure classification results to assign a particular one of a plurality of failure classifications to each die;

counting the number of die assigned to each of the plurality of failure classifications; and

computing a yield loss percentage for each of the plurality of failure classifications based on the number of die assigned to each of the plurality of failure classifications.

7. A method for classifying failures of integrated circuit dies, comprising:

analyzing failure data for each of a plurality of dies on a wafer with a plurality of failure classifiers to produce a corresponding plurality of failure classification results for each die, wherein the failure data for each die combines bin map failure data, electrical analysis data and physical failure data for the die; and

for the failure data for each die, analyzing the plurality of failure classification results to assign a particular one of a plurality of failure classifications to each die, wherein analyzing comprises analyzing the failure data for each die with at least one die level classifier to produce a die level classification result and with at least one wafer level classifier to produce a wafer level classification result, and analyzing the die level classification result and the wafer level classification result with a preference towards assigning a wafer level failure classification to the failure data when the wafer level classification result indicates presence of a wafer level failure for the die regardless of the die level classification result for that die.

8. A method for classifying failures of integrated circuit dies, comprising:

analyzing failure data for each of a plurality of dies on a wafer with a plurality of failure classifiers to produce a corresponding plurality of failure classification results for each die, wherein the failure data for each die combines bin map failure data, electrical analysis data and physical failure data for the die; and

for the failure data for each die, analyzing the plurality of failure classification results to assign a particular one of a plurality of failure classifications to each die, wherein analyzing comprises analyzing the failure data for each die with at least one die level classifier to produce a die level classification result and with at least one wafer level classifier to produce a wafer level classification result, wherein analyzing comprises analyzing the failure data for a die with a first die level classifier that analyzes data describing a spatial orientation of a failure density across a die, and analyzing the failure data for a die with a second die level classification that analyzes whether the die could not be sufficiently tested during wafer level testing.

9. A method for classifying failures of integrated circuit dies, comprising:

a. receiving a set of failure data for each of a plurality of integrated circuit dies, wherein the set of failure data for each die combines bin map failure data, electrical analysis failure data and physical failure data for the die;

b. analyzing each set of failure data with a die level classifier to produce a die level classification result indicating the degree to which the failure data contains a die level failure;

c. analyzing each set of failure data with a wafer level classifier to produce a wafer level classification result indicating the degree to which the failure data contains a wafer level failure; and

d. for each set of failure data, analyzing the die level classification result and the wafer level classification result to assign a particular one of a plurality of failure classifications for each integrated circuit die.

10. The method of claim 9, and further comprising receiving a set of training failure data for each of a plurality of known failures determined for a plurality of integrated circuit dies;

for each set of training failure data assigning a wafer level classification to the set of training failure data when the set of training failure data indicates a wafer level failure, generating a library of wafer level failure classifications from a plurality of sets of training failure data obtained for a plurality of integrated circuit dies; and

wherein (c) analyzing comprises analyzing the set of failure data with the wafer level classifier with reference to the wafer level classification library.

11. The method of claim 9, wherein the die level classifier employs a neural network model, and further comprising updating the neural network model with die level failure classifications from sets of training failure data that do not indicate a wafer level failure, wherein (c) analyzing comprises analyzing the set of failure data using the neural network model.

12. The method of claim 9, wherein (d) analyzing comprises analyzing the die level classification result and the wafer level classification result with a preference towards assigning a wafer level failure classification to the set of failure data when the wafer level classification result indicates a presence of a wafer level failure.

13. The method of claim 11, wherein (d) analyzing comprises analyzing the die level classification result and the wafer level classification result and assigning a die level failure classification to a set of failure data only when the wafer level classification result indicates that there is no presence of a wafer level signature.

14. The method of claim 9, and further comprising analyzing each set of failure data with an application level classifier to produce an application level classification result indicating the degree to which the set of failure data contains an application or functional level failure, and wherein (d) analyzing comprises analyzing the die level classification result, the wafer level classification result and the application level classification result to assign a wafer level classification to the set of failure data when the wafer level classification result indicates a presence of a wafer level signature regardless of the die level classification and application level classification result.

15. The method of claim 14, wherein (d) analyzing comprises assigning an application level classification to the set of failure data when the wafer level classification result does not indicate a presence of a wafer level signature and the application level classification result indicates existence of an application level failure regardless of the die level classification result.

16. The method of claim 14, wherein (d) analyzing comprises assigning a die level classification to the set of failure data when the wafer level classification result does not indicate a presence of a wafer level signature, the application level classification result does not indicate existence of an application level failure and the die level classification result indicates existence of a die level failure.

17. The method of claim 9, and further comprising counting the number of sets of failure data assigned to each of the plurality of failure classifications.

18. The method of claim 17, and further comprising computing a yield loss percentage for each of the plurality of failure classifications.

19. The method of claim 9, wherein (b) analyzing comprises analyzing each set of failure data with a first die level classifier that analyzes data describing a spatial orientation of a failure density across a die, and analyzing each set of failure data with a second die level classification that analyzes whether the die could not be sufficiently tested during wafer level testing.

20. A computer readable medium storing instructions, that when executed by a computer, cause the computer to classify failures of integrated circuit dies, comprising functions of:

a. receiving a set of failure data for each of a plurality of integrated circuit dies, wherein the set of failure data for each die combines bin map failure data, electrical analysis failure data and physical failure data for the die;

b. analyzing each set of failure data with at least one die level classifier to produce a die level classification result indicating the degree to which the failure data contains a die level failure and with at least one wafer level classifier to produce a wafer level classification result indicating the degree to which the failure data contains a wafer level failure; and

c. for each set of failure data, analyzing the die level classification result and the wafer level classification result to assign a particular one of a plurality of failure classifications for each integrated circuit die.

21. The computer readable medium of claim 20, and further comprising instructions, that when executed by said computer, cause said computer to perform, during an offline training phase, functions of:

receiving a set of training failure data for each of a plurality of known failures determined for a plurality of integrated circuit dies;

for each set of training failure data assigning a wafer level classification to the set of training failure data when the set of training failure data indicates a wafer level failure, generating a library of wafer level failure classifications from a plurality of sets of training failure data obtained for a plurality of integrated circuit dies; and

wherein the instructions for (b) analyzing comprises instructions for analyzing the set of failure data with the wafer level classifier with reference to the wafer level classification library.

22. The computer readable medium of claim 20, wherein the instructions for (b) analyzing comprise instructions that, when executed by said computer, cause said computer to execute the die level classifier using a neural network model, and further comprising instructions, that when executed by said computer, cause said computer to perform, during the offline training phase, functions of:

updating the neural network model with die level failure classifications from sets of training failure data that do not indicate a wafer level failure.

23. A system for classifying failures of integrated circuit dies, comprising:

a. a computing device;

b. a wafer level failure classification library that contains a plurality of wafer level failure classifications;

c. a die level classification model that contains data used to classify failure data to one of a plurality of die level failure classifications;

d. wherein the computing device, during an offline training phase;

analyzes a set of training failure data for each of a plurality of known failures determined for a plurality of semiconductor integrated circuit dies and for each set of training failure data assigns a wafer level classification to the set of training failure data when the set of training failure data indicates a wafer level failure and accordingly updates the wafer level classification library, and updates the die level classification model with die level failure classifications from sets of training failure data that do not indicate a wafer level failure; and

e. wherein for a set of failure data for each of a plurality of integrated circuit dies whose failure classification is not yet known, the computing device;

i. analyzes each set of failure data with the die level classification model to produce a die level classification result indicating the degree to which the failure data contains a die level failure;

ii. analyzes each set of failure data with a wafer level classifier using the wafer level classification library to produce a wafer level classification result indicating the degree to which the failure data contains a wafer level failure; and

iii. for each set of failure data, analyzing the die level classification result and the wafer level classification result to assign a particular one of a plurality of failure classifications for each integrated circuit die.

24. The system of claim 23, wherein the computing device analyzes the die level classification result and the wafer level classification result with a preference towards assigning a wafer level failure classification to the set of failure data when any the wafer level classification result indicates a presence of a wafer level failure.

25. The system of claim 23, wherein the computing device further counts the number of sets of failure data assigned to each of the plurality of failure classifications, and computes a yield loss percentage for each of the plurality of failure classifications.