Supplemental Communication Interface

• US 20080147923A1
• Filed: 10/10/2006
• Published: 06/19/2008
• Est. Priority Date: 10/10/2006
• Status: Active Grant

• Current Assignee: Atmel Rousset S.A.S. (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Parlange, Dominique, Renahy, Florent
• Granted Patent: US 7,958,291 B2
• Time in Patent Office: Days
• US Class Current: 710/62
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

In some implementations, an apparatus includes a first interface having a communication channel through which data is transmitted to or received from a target device and a first control register that is configured to control, based at least in part on its contents, transmission or reception of data through the communication channel; a second interface having a second control register that is configured to control, based at least in part on its contents, transmission or reception of data through the communication channel; and a circuit that harmonizes contents of the first control register and the second control register, such that an external controller can control transmission or reception of data through the communication channel by providing control data in a first format to the first control register or by providing alternate control data in a second different format to the second control register.

Claims

1. An apparatus comprising:

a first interface having a communication channel through which data is transmitted to or received from a target device; and

a first control register that is configured to control, based at least in part on its contents, transmission or reception of data through the communication channel;

a second interface having a second control register that is configured to control, based at least in part on its contents, transmission or reception of data through the communication channel; and

a circuit that harmonizes contents of the first control register and the second control register, such that an external controller can control transmission or reception of data through the communication channel by providing control data in a first format to the first control register or by providing alternate control data in a second different format to the second control register.

2. The apparatus of claim 1, wherein the communication channel comprises a physical serial communication link.

3. The apparatus of claim 2, wherein the physical serial communication link implements serial communication between two or more devices, the serial communication substantially adhering to a serial peripheral interface (SPI) protocol, an inter-integrated circuit (I²C) protocol, a 1-wire bus protocol, a system management bus (SMBus) protocol, or a proprietary serial communication protocol.

4. The apparatus of claim 1, wherein the first interface further comprises a buffer that is configured to store data to be transmitted to the target device or data that has been received from the target device.

5. The apparatus of claim 4, wherein the second interface comprises a pointer that identifies a portion of the buffer.

6. The apparatus of claim 5, wherein the second interface comprises a buffer control circuit that alters the pointer in response to subsequent, different contents of the second control register.

7. The apparatus of claim 4, wherein the buffer includes a plurality of portions, each portion corresponding to a discrete quantum of data that can be processed by the communication channel at one time.

8. The apparatus of claim 7, wherein the quantum of data is one byte.

9. The apparatus of claim 7, wherein each portion of the plurality of portions is memory-mapped to a discrete address value and individually addressable through the discrete address value by the external controller.

10. The apparatus of claim 1, wherein the first interface is a discrete, physical integrated circuit that is included in the apparatus.

11. The apparatus of claim 1, wherein the first interface is a preconfigured portion of an integrated circuit or a programmable device selected from the group consisting of programmable logic devices (PLDs) and field programmable gate arrays (FPGAs).

12. The apparatus of claim 1, wherein each of the first and second interface comprises additional registers, wherein the second interface comprises fewer total registers than the first interface.

13. The apparatus of claim 1, wherein the second interface is configured to automate more functions in hardware than can be automated by the first interface.

14. The apparatus of claim 13, wherein the second interface is configured such that less programming code is needed to interact directly with the second interface to effect transmission of data than is needed to interact directly with the first interface to effect a same transmission of data.

15. The apparatus of claim 13, wherein the second interface is configured such that less programming code is needed to interact directly with the second interface to process a reception of data than is needed to interact directly with the first interface to process a same reception of data.

16. An apparatus comprising:

a first interface having a communication channel through which data is transmitted to or received from a target device; and

a first status register that provides status information about the first interface;

a second interface having a second status register that provides secondary status information about the first interface; and

a circuit that harmonizes contents of the first status register and second status register, such that an external controller can receive status information from the first status register in a first format or secondary status information from the second status register in a second format.

17. The apparatus of claim 16, wherein the first interface further comprises a buffer that is configured to store data to be transmitted to the target device or data that has been received from the target device.

18. The apparatus of claim 17, wherein the buffer includes a plurality of portions, each portion corresponding to a discrete quantum of data that can be processed by the communication channel at one time.

19. The apparatus of claim 18, wherein the quantum of data is one byte.

20. The apparatus of claim 19, wherein each portion of the plurality of portions is memory-mapped to a discrete address value and individually addressable through the discrete address value by the external controller.

21. The apparatus of claim 20, wherein the second status register is configured to directly provide at least a portion of the discrete address value when the secondary status information contained in the second status register relates to a buffer portion corresponding to the discrete address value.

22. An apparatus comprising:

a first interface having a communication channel through which data is transmitted to or received from a target device;

a first control register that is configured to control, based at least in part on its contents, transmission or reception of data through the communication channel; and

a first status register that provides status information about the first interface;

a second interface having a second control register that is configured to control, based at least in part on its contents, transmission or reception of data through the communication channel; and

a second status register that provides secondary status information about the first interface; and

a circuit that harmonizes contents of the first control register and the second control register, and harmonizes contents of the first status register and second status register such that an external controller can control transmission or reception of data through the communication channel by providing control data in a first format to the first control register or by providing alternate control data in a second different format to the second control register, and such that the external controller can receive status information from the first status register in a first format or secondary status information from the second status register in a second format.

23. An apparatus comprising:

an interface having a control register that is configured to control, based at least in part on its contents, transmission or reception of data through a communication channel; and

a status register that provides status information about the interface; and

a circuit that is configured to harmonize contents of at least one of the control register and another register or the status register and the other register;

wherein the other register is associated with the communication channel, such that an external controller can a) control transmission or reception of data through the communication channel by providing control data in a first format to the control register or providing alternative control information in a second format to the other register or b) receive status information from the status register in a first format or alternate status information from the other register in the second format.

24. The apparatus of claim 23, further comprising a second interface, wherein the second interface includes the other register.

25. The apparatus of claim 24, wherein the other register comprises a control portion and a status portion.

26. The apparatus of claim 25, wherein the circuit is configured to harmonize the contents of the control register with the control portion and harmonize the contents of the status register with the status portion.

27. The apparatus of claim 26, wherein the interface is configured to automate more functions in hardware than can be automated by the second interface.

28. The apparatus of claim 26, wherein the interface is configured such that less programming code is needed to interact directly with the interface to effect transmission of data than is needed to interact directly with the second interface to effect a same transmission of data.

29. The apparatus of claim 24, wherein the second interface is a discrete, physical integrated circuit that is included in the apparatus.

30. The apparatus of claim 24, wherein the second interface is a preconfigured portion of an integrated circuit or a programmable device selected from the group consisting of programmable logic devices (PLDs) and field programmable gate arrays (FPGAs).

31. The apparatus of claim 23, wherein the communication channel comprises a physical serial communication link.

32. A method comprising:

controlling a first interface having a communication channel through which data is transmitted to or received from a target device, the controlling including controlling transmission or reception of data through the communication channel based at least in part on control information formatted according to a first format; and

controlling a second interface, the second interface configured for transmission or reception of data through the communication channel, the controlling including controlling transmission or reception of data through the communication channel based at least in part on control information formatted according to a second different format.

33. The method of claim 32, wherein the second format is configured such that a processor can execute less code to identify a memory portion associated with the transmission or reception of data from the second interface than from the first interface.

34. The method of claim 32, further comprising harmonizing a first register associated with the first interface with a second register associated with the second interface.

35. A method comprising:

receiving a digital message from a communication channel;

storing the message in a memory buffer;

storing, in a first status register and in a first format, status information corresponding to the stored message; and

storing, in a second status register and in a second format, supplemental status information corresponding to the stored message;

wherein the second format is configured such that a processor can execute less code to identify the memory buffer from the supplemental status information than from the status information.

36. The method of claim 35, wherein receiving the digital message comprises receiving the digital message serially, the method further comprising converting the received digital message to a parallel format.

37. The method of claim 35, further comprising extracting a data component from the message.

38. The method of claim 37, wherein extracting the data component comprises at least one of removing header or trailer information, decoding at least a portion of the message or performing error checking on at least a portion of the message.

39. The method of claim 35, further comprising asserting an interrupt signal upon storing the status information or the supplemental status information.