High Performance Flash Memory Devices (FMD)

• US 20080147968A1
• Filed: 01/21/2008
• Published: 06/19/2008
• Est. Priority Date: 01/06/2000
• Status: Active Grant

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Shen, Ming-Shiang, Lee, Charles C., Chow, David Q., Ma, Abraham Chih-Kang, Yu, I-Kang
• Granted Patent: US 7,827,348 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

High performance flash memory devices (FMD) are described. According to one exemplary embodiment of the invention, a high performance FMD includes an I/O interface, a FMD controller, and at least one non-volatile memory module along with corresponding at least one channel controller. The I/O interface is configured to connect the high performance FMD to a host computing device The FMD contoller is configured to control data transfer (e.g., data reading, data writing/programming, and data erasing) operations between the host computing device and the non-volatile memory module. The at least one non-volatile memory module, comprising one or more non-volatile memory chips, is configured as a secondary storage for the host computing device. The at least one channel controller is configured to ensure proper and efficient data transfer between a set of data buffers located in the FMD controller and the at least one non-volatile memory module.

Claims

1. A high performance flash memory device (FMD) comprising:

a FMD interface configured to provide data input and output to a host computer system;

at least one non-volatile memory module having one or more non-volatile memory chips that are arranged in a plurality of vertical groups and in a plurality of horizontal rows such that each of the vertical groups and each of the horizontal rows having one of said one or more non-volatile memory chips overlapped, wherein number of the non-volatile memory chips in said each of the vertical groups is equal to number of the plurality of horizontal rows; and

a FMD controller configured to control data transmission between said at least one non-volatile memory module and the host computer system via said FMD interface, said FMD controller comprises a microcontroller, a plurality of parallel data buffers and a plurality of independent data channels, each of the parallel data buffers is divided into a plurality of sub-buffers, each of the sub-buffers is connected to corresponding one of the parallel data channels, wherein each of the data channels connects to respective one of the horizontal rows and wherein said data transmission is conducted in parallel via the independent data channels in one of at least one data interleaving scheme.

2. The high performance FMD of claim 1 further comprises at least one channel controller configured to control data transfer between the plurality of the parallel data buffers and said at least one non-volatile memory module.

3. The high performance FMD of claim 2, wherein said at least one channel controller is integrated within the FMD controller.

4. The high performance FMD of claim 2, wherein said at least one channel controller is included with said at least one non-volatile memory module.

5. The high performance FMD of claim 2, wherein said FMD interface comprises Advanced Technology Attachment (ATA), Serial ATA (SATA), Small Computer System Interface (SCSI), Universal Serial Bus (USB), Peripheral Component Interconnect (PCI) Express, ExpressCard, fiber channel Interface, optical connection interface circuit, Secure Digital.

6. The high performance FMD of claim 2, wherein each of said one or more volatile memory chips include two dies stackedly attached to each other using a stacked chip scale package technology.

7. The high performance FMD of claim 6, wherein the dies are wired in such manner that I/O pins and control pin are shared while ready/busy and chip select pins are separately selectable.

8. The high performance FMD of claim 7, wherein each of the dies includes at least two planes, each of the planes comprises an independently accessible register.

9. The high performance FMD of claim 7, wherein the respective chip select pin of all of the non-volatile memory chips is wired together such that a particular chip enable signal from said at least one channel controller activates corresponding one of the dies of all of the non-volatile memory chips in said each of the vertical groups.

10. The high performance FMD of claim 7, wherein the ready/busy pin of both of the dies of all of the non-volatile memory chips in said each of the vertical groups is wired in such manner that a ready/busy signal for a particular one group of the vertical groups is detectable as a whole at said at least one channel controller.

11. The high performance FMD of claim 6, wherein each of the dies is a single-level cell flash memory die or a multi-level cell flash memory die.

12. The high performance FMD of claim 2, wherein said FMD controller further comprises a plurality of command registers, a control register, a data register, a high-low byte filter, a data multiplexer, a command decoder, a data dispatching unit, an error correction code generator, a plurality of task file registers,

13. The high performance FMD of claim 12, wherein the command decoder is configured to decode commands and control signals received at the command registers and the control register, respectively, and the commander decoder is coupled to the data multiplexer, the microcontroller and the plurality of task file registers to process the decoded commands.

14. The high performance FMD of claim 12, wherein the data register is configured to receive information from the FMD interface, then, if necessary, the received information is separated into high-byte and low byte by the high-low byte filter before sending to the task file registers via to be processed via the data multiplexer.

15. The high performance FMD of claim 14, wherein the received information include, but are not necessarily limited to, logical address, data count, high and low bytes of a buffer address pointer, and high and low bytes of a corresponding data.

16. The high performance FMD of claim 15, wherein the data dispatching unit fills the corresponding data into the plurality of parallel data buffers using the received information.

17. The high performance FMD of claim 16, wherein the corresponding data is organized in said one of the at least one data interleaving scheme.

18. The high performance FMD of claim 2, further comprises a cache configured for holding recently transferred data.

19. The high performance FMD of claim 18, wherein the cache comprises hierarchical cache made of static random access memory (SRAM) as a first level cache and dynamic RAM (DRAM) as a second level cache.

20. A method of data reading operations in high performance flash memory device (FMD) having at least two groups of at least one non-volatile memory chip, each of the non-volatile memory chips includes at least two dies, each of the dies includes two planes, the dies share input/output and control buses but are selectable individually, said method comprising:

(a1) receiving a data read request;

(a2) loading a first chunk of data to respective register of a first plane of a first die of the first group of non-volatile memory chips, and loading a fifth chunk of data to respective register of a first plane of a first die of the second group;

(a3) filling the first chunk of data from the respective register of the first plane of the first die of the first group into a first data buffer;

(a4) while the first chunk of data in the first data buffer is transferred to a host according to a predefined data interleaving scheme, loading a second chunk of data to respective register of a second plane of the first die of the first group, and then filling the second chunk of data from the respective register of the second plane of the first die of the first group into a second data buffer;

(a5) while the second chunk of data in the second data buffer is transferred to the host according to the predefined data interleaving scheme, loading a third chunk of data to respective register of a first plane of a second die of the first group, and then filling the third chunk of data from the respective register of the first plane of the second die of the first group into the first data buffer;

(a6) while the third chunk of data in the first data buffer is transferred to the host according to the predefined data interleaving scheme, loading a fourth chunk of data to respective register of a second plane of the second die of the first group, and then filling the fourth chunk of data from the respective register of the second plane of the second die of the first group into the second data buffer;

(a7) while the fourth chunk of data in the second data buffer is transferred to the host according to the predefined data interleaving scheme, loading a new first chunk of data to respective register of the first plane of the first die of the first group, and filling the fifth chunk of data from the respective register of the first plane of the first die of the second group into the first data buffer;

(a8) while the fifth chunk of data in the first data buffer is transferred to the host according to the predefined data interleaving scheme, loading a sixth chunk of data to respective register of a second plane of the first die of the second group, and then filling the sixth chunk of data from the respective register of the second plane of the first die of the second group into the second data buffer;

(a9) while the sixth chunk of data in the second data buffer is transferred to the host according to the predefined data interleaving scheme, loading a seventh chunk of data to respective register of a first plane of a second die of the second group, and then filling the seventh chunk of data from the respective register of the first plane of the second die of the second group into the first data buffer;

(a10) while the seventh chunk of data in the first data buffer is transferred to the host according to the predefined data interleaving scheme, loading for an eighth chunk of data to respective register of a second plane of the second die of the second group, and then filling the eighth chunk of data from the respective register of the second plane of the second die of the second group into the second data buffer;

(a11) while the eighth chunk of data in the second data buffer is transferred to the host according to the predefined data interleaving scheme, loading a new fifth chunk of data to respective register of the first plane of the first die of the second group; and

(a12) repeating steps (a3)-(a10) until said data read request has been fulfilled.

21. The method of claim 20, wherein each of the first and second data buffers includes corresponding numbers of sub-buffers matching number of the at least one non-volatile memory chip in each of the first and second groups.

22. The method of claim 21, wherein the predefined data interleaving scheme further comprising:

partitioning each of the sub-buffers into at least one cluster;

filling data into a first cluster of the at least one cluster of each of the sub-buffers in the first data buffer then a first cluster of the at least one cluster of said each of the sub-buffers in the second data buffer sequentially; and

if required, filling data into a next cluster of the at least one cluster of said each of the sub-buffers in the first data buffer then a next cluster of the at least one cluster of said each of the sub-buffers in the second data buffer sequentially, until all of the data buffers have been filled up.

23. The method of claim 22, wherein each of the one or more clusters comprises a maximum size equaling to size of the sub-buffer and a minimum size equaling to size of a data sector.

24. A method of data programming operations in high performance flash memory device (FMD) having at least two groups of at least one non-volatile memory chips, each of the non-volatile memory chips includes at least two dies, each of the dies includes two planes, the dies share input/output and control buses but are selectable individually, said method comprising:

(b1) receiving a data program request;

(b2) filling a first chunk of data into a first data buffer in a predefined data interleaving scheme from a host;

(b3) moving the first chunk of data from the first data buffer into respective register of a first plane of a first die of a first group of non-volatile memory chips;

(b4) while the first chunk of data is written from the respective register to corresponding location of the non-volatile memory chips, setting read/busy signal of all of the non-volatile memory chips in the first group to busy and filling a second chunk of data into a second data buffer in the predefined data interleaving scheme from the host;

(b5) moving the second chunk of data from the second data buffer into respective register of a second plane of the first die of the first group;

(b6) while the second chunk of data is written from the respective register to corresponding location of the non-volatile memory chips, setting read/busy signal of all of the non-volatile memory chips in the first group to busy and filling a third chunk of data into the first data buffer in the predefined data interleaving scheme from the host;

(b7) moving the third chunk of data from the first data buffer into respective register of a first plane of a second die of the first group;

(b8) while the third chunk of data is written from the respective register to corresponding location of the non-volatile memory chips, setting read/busy signal of all of the non-volatile memory chips in the first group to busy and filling a fourth chunk of data into the second data buffer in the predefined data interleaving scheme from the host;

(b9) while the fourth chunk of data is written from the respective register to corresponding location of the non-volatile memory chips, setting read/busy signal of all of the non-volatile memory chips in the first group to busy and filling a fifth chunk of data into the first data buffer in the predefined data interleaving scheme from the host;

(b10) moving the fifth chunk of data from the first data buffer into respective register of a first plane of a first die of a second group;

(b11) while the fifth chunk of data is written from the respective register to corresponding location of the non-volatile memory chips, setting read/busy signal of all of the non-volatile memory chips in the second group to busy and filling a sixth chunk of data into the second data buffer in the predefined data interleaving scheme from the host;

(b12) moving the sixth chunk of data from the second data buffer into respective register of a second plane of the first die of the second group;

(b13) while the sixth chunk of data is written from the respective register to corresponding location of the non-volatile memory chips, setting read/busy signal of all of the non-volatile memory chips in the second group to busy and filling a seventh chunk of data into the first data buffer in the predefined data interleaving scheme from the host;

(b14) moving the seventh chunk of data from the first data buffer into respective register of a first plane of a second die of the second group;

(b15) while the seventh chunk of data is written from the respective register to corresponding location of the non-volatile memory chips, setting read/busy signal of all of the non-volatile memory chips in the second group to busy and filling an eighth chunk of data into the second data buffer in the predefined data interleaving scheme from the host;

(b16) moving the eighth chunk of data from the second data buffer into respective register of a second plane of the second die of the second group;

(b17) while the eighth chunk of data is written from the respective register to corresponding location of the non-volatile memory chips, setting read/busy signal of all of the non-volatile memory chips in the second group to busy and filling a new first chunk of data into the first data buffer if required; and

(b18) repeating steps (b3)-(b17) until the data programming request has been fulfilled.

25. The method of claim 24, wherein each of the first and second data buffers includes corresponding numbers of sub-buffers matching number of the at least one non-volatile memory chip in each of the first and second groups.

26. The method of claim 25, wherein the predefined data interleaving scheme further comprising:

partitioning each of the sub-buffers into at least one cluster;

filling data into a first cluster of the at least one cluster of each of the sub-buffers in the first data buffer then a first cluster of the at least one cluster of said each of the sub-buffers in the second data buffer sequentially; and

if required, filling data into a next cluster of the at least one cluster of said each of the sub-buffers in the first data buffer then a next cluster of the at least one cluster of said each of the sub-buffers in the second data buffer sequentially, until all of the data buffers have been filled up.

27. The method of claim 26, wherein each of the one or more clusters comprises a maximum size equaling to size of the sub-buffer and a minimum size equaling to size of a data sector.