Method for improving reliability of multi-core processor computer

• US 20080148015A1
• Filed: 03/30/2007
• Published: 06/19/2008
• Est. Priority Date: 12/19/2006
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Takamoto, Yoshifumi, Horie, Toru
• Granted Patent: US 7,937,615 B2
• Time in Patent Office: Days
• US Class Current: 712/203
• CPC Class Codes: G06F 11/2025 using centralised failover control functionality
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space

Abstract

In a system including a plurality of multi-core processors, a table for managing the processors and cores owned by the processors is provided and a single virtual server is formed by using cores owned by different processors when generating the virtual server. According to the number owned by processors, the number of processors is varied. If a fault preecho in a processor is detected, control is exercised so as not to deliver an execution schedule of a virtualization mechanism to the processor in which the fault preecho has been detected. In a system including a plurality of multi-core processors, arithmetic cores owned by a plurality of different processors are assigned to processing of a process or thread in an operating system. In a system including a plurality of multi-core processors, arithmetic cores owned by a plurality of different processors are assigned to the operating system.

Claims

1. In a virtualization environment in which a virtualization mechanism for generating and controlling a virtual server operates in a server including a plurality of processors each having a plurality of arithmetic cores,

a multi-core processor reliability improving method comprising the steps of:

referring to an arithmetic core management table which manages correspondence between the processors and the arithmetic cores, when generating the virtual server; and

then assigning arithmetic cores owned by the different processors to the virtual server.

2. In a virtualization environment in which a virtualization mechanism for generating and controlling a virtual server operates in a server including a plurality of processors each having a plurality of arithmetic cores and the virtualization mechanism is managed by a management server,

a multi-core processor reliability improving method, wherein

the management server comprises an arithmetic core management table which manages correspondence between the processors and the arithmetic cores, and

the multi-core processor reliability improving method comprising the steps of:

referring to an arithmetic core management table which manages correspondence between the processors and the arithmetic cores, when generating the virtual server; and

then assigning arithmetic cores owned by the different processors to the virtual server.

3. The multi-core processor reliability improving method according to claim 2, wherein

the arithmetic core management table stores the number of arithmetic cores owned by each processor, and

as the number of arithmetic cores owned by a processor becomes large, the number of processors assigned to the virtual server is made large.

4. The multi-core processor reliability improving method according to claim 2, wherein if the numbers of arithmetic cores owned by the processors are different, arithmetic cores in processors that are the same in the number of owned arithmetic cores are assigned to the virtual server preferentially.

5. The multi-core processor reliability improving method according to claim 2, wherein

a user interface in the management server comprises an order part where one of at least reliability-weighted assignment and performance-weighted assignment is ordered,

if the reliability-weighted is ordered, assignment of arithmetic cores to the virtual server is distributed among a plurality of processors, and

if the performance-weighted is ordered, arithmetic cores owned by same processor are assigned preferentially.

6. In a virtualization environment in which a virtualization mechanism for generating and controlling a virtual server operates in a server including a plurality of processors each having a plurality of arithmetic cores and the virtualization mechanism is managed by a management server,

a multi-core processor reliability improving method, wherein

the virtualization mechanism comprises a fault preecho detection mechanism for detecting a fault preecho in the processors, and

if the fault preecho detection mechanism has detected a fault preecho in a processor or arithmetic core, the management server changes an execution schedule so as to prevent the virtualization mechanism from being executed in the processor or arithmetic core in which the fault preecho has been detected.

7. The multi-core processor reliability improving method according to claim 6, wherein

the management server comprises a counteraction table associated with regions of the processors to be used when a fault preecho is detected, and

when a fault preecho is detected, the processor or the arithmetic core is alternated on the basis of the counteraction table.

8. The multi-core processor reliability improving method according to claim 7, wherein as for the alternation of the processor or the arithmetic core, the alternation is conducted after the arithmetic core is changed over to a step execution mode in which execution can be stopped by taking an instruction as unit.

9. The multi-core processor reliability improving method according to claim 7, wherein if the processor comprises arithmetic cores of different kinds, arithmetic cores of a kind that is small in number are alternated preferentially when a fault preecho is detected.

10. A multi-core processor reliability improving method used in a server including a plurality of processors each having a plurality of arithmetic cores, wherein

arithmetic cores owned by a plurality of different processors are assigned to processing of a process or thread in an operating system.

11. A multi-core processor reliability improving method used in a server including a plurality of processors each having a plurality of arithmetic cores, a plurality of operating systems being operated in the server, wherein

arithmetic cores owned by a plurality of different processors are assigned to the operating systems.