HIGH-SPEED PROGRAMMING OF MEMORY DEVICES

• US 20080148115A1
• Filed: 12/17/2007
• Published: 06/19/2008
• Est. Priority Date: 12/17/2006
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Shalvi, Ofir, Sokolov, Dotan
• Granted Patent: US 7,900,102 B2
• Time in Patent Office: Days
• US Class Current: 714/719
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

A method for operating a memory that includes a plurality of analog memory cells includes storing data in a first group of the memory cells by writing respective first cell values to the memory cells in the first group. After storing the data, respective second cell values are read from the memory cells in the first group, and differences are found between the respective first and second cell values for each of one or more of the memory cells in the first group. The differences are processed to produce error information, and the error information is stored in a second group of the memory cells.

Claims

1. A method for operating a memory that includes a plurality of analog memory cells, comprising:

storing data in a first group of the memory cells by writing respective first cell values to the memory cells in the first group;

after storing the data, reading respective second cell values from the memory cells in the first group, and finding differences between the respective first and second cell values for each of one or more of the memory cells in the first group;

processing the differences to produce error information; and

storing the error information in a second group of the memory cells.

2. The method according to claim 1, wherein the second group of the memory cells is different from the first group.

3. The method according to claim 1, wherein writing the first cell values and reading the second cell values comprise programming the memory cells of the first group in an iterative Program and Verify (P&

V) process.

4. The method according to claim 1, wherein processing the differences comprises quantizing the differences by mapping the differences to a finite set of difference indications, and wherein storing the error information comprises storing the quantized differences.

5. The method according to claim 4, wherein processing the differences comprises adaptively controlling a size of the produced error information responsively to the quantized differences.

6. The method according to claim 4, wherein storing the data comprises selecting the first cell values from a set of nominal values, and wherein the difference indications indicate whether the nominal values corresponding to the read second cell values differ from the respective nominal values corresponding to the written first cell values.

7. The method according to claim 6, wherein, for a given first cell value that corresponds to a first nominal value and a given second cell value that corresponds to a second nominal value, the difference indications comprise at least one of:

a first indication indicating that the first nominal value is lower than and adjacent to the second nominal value in the set of the nominal values;

a second indication indicating that the first nominal value is greater than and adjacent to the second nominal value in the set of the nominal values; and

a third indication indicating that the first nominal value is equal to the second nominal value.

8. The method according to claim 1, wherein storing the error information comprises compressing the error information and storing the compressed error information.

9. The method according to claim 1, wherein storing the error information comprises encoding the error information with an Error Correction Code (ECC) and storing the encoded error information.

10. The method according to claim 1, wherein storing the error information comprises storing indices of the memory cells of the first group in which the differences were found.

11. The method according to claim 1, wherein reading the second cell values and finding the differences are performed immediately after writing the first cell values.

12. The method according to claim 1, wherein reading the second cell values and finding the differences are performed a predetermined time interval after writing the first cell values.

13. The method according to claim 1, wherein the memory cells in the first group are subject to interference from a third group of the memory cells, and wherein reading the second cell values and finding the differences are performed after the memory cells in the third group have been programmed.

14. The method according to claim 1, wherein reading the second cell values and finding the differences are performed responsively to an event.

15. The method according to claim 1, and comprising retrieving the stored data by retrieving the error information from the second group of the memory cells, reading third cell values from the cells in the first group, and processing the third cell values responsively to the retrieved error information to produce corrected data.

16. The method according to claim 15, wherein retrieving the stored data comprises making an attempt to reconstruct the data from the third cell values without the error information, and retrieving the error information and processing the third cell values responsively to the retrieved error information upon a failure of the attempt.

17. The method according to claim 15, wherein storing the data comprises encoding the data with a code that detects errors in the data, and wherein retrieving the stored data comprises detecting the errors in the data using the code and updating the error information based on the third cell values when a number of the detected errors meets a predetermined condition.

18. The method according to claim 17, wherein updating the error information is performed when the number of the detected errors exceeds a predetermined threshold.

19. The method according to claim 1, wherein storing the data comprises programming the first memory cells using first programming parameters such that the error information has a first size, and comprising, after storing the error information:

reading the error information from the second group of the memory cells, reading third cell values from the cells in the first group, and reconstructing the data by processing the third cell values responsively to the read error information; and

re-programming the data using second programming parameters so as to produce refined error information having a second size, which is smaller than the first size.

20. Apparatus for operating a memory that includes a plurality of analog memory cells, comprising:

Read/Write (R/W) circuitry, which is coupled to store data in a first group of the memory cells by writing respective first cell values to the memory cells in the first group and, after storing the data, to read respective second cell values from the analog memory cells in the first group; and

a processor, which is configured to find differences between the respective first and second cell values for each of one or more of the memory cells in the first group, to process the differences to produce error information and to store the error information in a second group of the memory cells.

21. The apparatus according to claim 20, wherein the second group of the memory cells is different from the first group.

22. The apparatus according to claim 20, wherein the R/W circuitry is coupled to program the memory cells of the first group in an iterative Program and Verify (P&

V) process.

23. The apparatus according to claim 20, wherein the processor is configured to quantize the differences by mapping the differences to a finite set of difference indications, and to store the quantized differences in the second group of the memory cells.

24. The apparatus according to claim 23, wherein processing the differences comprises adaptively controlling a size of the produced error information responsively to the quantized differences.

25. The apparatus according to claim 23, wherein the R/W circuitry is coupled to select the first cell values from a set of nominal values, and wherein the difference indications indicate whether the nominal values corresponding to the read second cell values differ from the respective nominal values corresponding to the written first cell values.

26. The apparatus according to claim 25, wherein, for a given first cell value that corresponds to a first nominal value and a given second cell value that corresponds to a second nominal value, the difference indications comprise at least one of:

a first indication indicating that the first nominal value is lower than and adjacent to the second nominal value in the set of the nominal values;

a second indication indicating that the first nominal value is greater than and adjacent to the second nominal value in the set of the nominal values; and

a third indication indicating that the first nominal value is equal to the second nominal value.

27. The apparatus according to claim 20, wherein the processor is configured to compress the error information and to store the compressed error information.

28. The apparatus according to claim 20, wherein the R/W circuitry is coupled to compare the respective first and second cell values to produce the differences, to compress the differences and to send the compressed differences to the processor.

29. The apparatus according to claim 20, wherein the processor is configured to encode the error information with an Error Correction Code (ECC) and to store the encoded error information.

30. The apparatus according to claim 20, wherein the processor is configured to store indices of the memory cells of the first group in which the differences were found.

31. The apparatus according to claim 20, wherein the processor and the R/W circuitry are configured to read the second cell values and to find the differences immediately after writing the first cell values.

32. The apparatus according to claim 20, wherein the processor and the R/W circuitry are configured to read the second cell values and to find the differences a predetermined time interval after writing the first cell values.

33. The apparatus according to claim 20, wherein the memory cells in the first group are subject to interference from a third group of the memory cells, and wherein the processor and the R/W circuitry are configured to read the second cell values and to find the differences after the memory cells in the third group have been programmed.

34. The apparatus according to claim 20, wherein the processor and the R/W circuitry are configured to read the second cell values and to find the differences responsively to an event.

35. The apparatus according to claim 20, wherein the processor is configured to retrieve the stored data by retrieving the error information from the second group of the memory cells, reading third cell values from the cells in the first group, and processing the third cell values responsively to the retrieved error information to produce corrected data.

36. The apparatus according to claim 35, wherein the processor is configured to make an attempt to reconstruct the data from the third cell values without the error information, and to retrieve the error information and process the third cell values responsively to the retrieved error information upon a failure of the attempt.

37. The apparatus according to claim 35, wherein the processor is configured to encode the data with a code that detects errors in the data, to store the encoded data in the first group of the memory cells, and, when retrieving the stored data, to detect the errors in the data using the code and to update the error information based on the third cell values when the number of the detected errors meets a predetermined condition.

38. The apparatus according to claim 37, wherein the processor is configured to update the error information when the number of the detected errors exceeds a predetermined threshold.

39. The apparatus according to claim 29, wherein the processor is configured to run a background task that finds the differences and produces the error information.

40. The apparatus according to claim 20, wherein the processor is configured to program the first memory cells using first programming parameters such that the error information has a first size, and, after storing the error information, to read the error information from the second group of the memory cells, to read third cell values from the cells in the first group, to reconstruct the data by processing the third cell values responsively to the read error information, and to re-program the data using second programming parameters so as to produce refined error information having a second size, which is smaller than the first size.

41. Apparatus for data storage, comprising:

a memory, which comprises a plurality of analog memory cells;

Read/Write (R/W) circuitry, which is coupled to store data in a first group of the memory cells by writing respective first cell values to the memory cells in the first group and, after storing the data, to read respective second cell values from the analog memory cells in the first group; and

a processor, which is configured to find differences between the respective first and second cell values for each of one or more of the memory cells in the first group, to process the differences to produce error information and to store the error information in a second group of the memory cells.