METHOD AND SYSTEM FOR DETECTING AND CORRECTING ERRORS WHILE ACCESSING MEMORY DEVICES IN MICROPROCESSOR SYSTEMS

• US 20080148124A1
• Filed: 02/05/2008
• Published: 06/19/2008
• Est. Priority Date: 06/04/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Paul Yang Lu, Yan Zhang, Yue Chen
• Inventors: Zhang, Yan, Chen, Yue, Lu, Paul Yang
• Granted Patent: US 8,335,960 B2
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems

Abstract

Systems and methods for ensuring data integrity in a data processing system are disclosed. The method may include monitoring when data for a specified device is available for error correction code generation. A new error correction code may be generated in hardware for the data, based on the indicated size of the data. Detected errors may be corrected in software, based on the generated new error correction code. A first indication of the specified device, a second indication of the data and a third indication of a size of the data may be received during the monitoring. The method may also include indicating when the generating of the new error correction code for a specified number of accesses for at least a portion of the data is complete, and enabling or disabling the error correction code generation. The enabling and/or the disabling may be accomplished via an enable signal.

Claims

1-72. -72. (canceled)

73. A method for ensuring data integrity in a data processing system, the method comprising:

monitoring when data for a specified device is available for error correction code generation;

generating new error correction code in hardware for said data based on said indicated size of said data; and

correcting detected errors in software based on said generated new error correction code.

74. The method according to claim 73, comprising receiving a first indication of said specified device, a second indication of said data and a third indication of a size of said data, during said monitoring.

75. The method according to claim 73, comprising indicating when said generating of said new error correction code for a specified number of accesses for at least a portion of said data is complete.

76. The method according to claim 73, comprising enabling or disabling said error correction code generation.

77. The method according to claim 74, wherein said enabling and said disabling is accomplished via an enable signal.

78. The method according to claim 74, wherein said first indication comprises a device selection signal.

79. The method according to claim 74, wherein said second indication is a data ready signal.

80. The method according to claim 74, wherein said third indication of said size of said data is a data size signal.

81. The method according to claim 75, comprising counting said specified number of accesses.

82. The method according to claim 75, comprising controlling said specified number of accesses by a page size setting.

83. The method according to claim 73, comprising specifying a page counter that indicates bytes of said data that are processed.

84. The method according to claim 81, comprising generating an interrupt when said page counter indicates that all bytes are processed.

85. The method according to claim 73, comprising generating a signal that indicates when said generation of said new error correction code is complete.

86. The method according to claim 73, comprising determining whether data access for said data is a read access or a write access.

87. The method according to claim 86, comprising:

deactivating error code generation for said data; and

if said data access is a write operation, writing said newly generated error correction code to external memory.

88. The method according to claim 86, comprising:

deactivating error correction code generation for said data; and

if said data access is a read operation, reading newly generated error correction code and reading stored error correction code corresponding to read data.

89. The method according to claim 88, comprising checking integrity of said read data.

90. The method according to claim 89, comprising comparing said newly generated error correction code with a stored error correction code corresponding to said read data.

91. The method according to claim 90, comprising determining whether said newly generated error correction code matches said stored error correction code.

92. The method according to claim 91, comprising determining whether said error correction code is incorrect, if said newly generated error correction code does not match said stored error correction code.

93. The method according to claim 92, comprising determining whether an error is correctable, if said error correction code is not in error.

94. The method according to claim 93, comprising correcting said error, if said error is correctable.

95. The method according to claim 93, comprising reporting said error, if said error is not correctable.

96. A machine-readable storage, having stored thereon a computer program having at least one code section for ensuring data integrity in a data processing system, the at least one code section executable by a machine for causing the machine to perform the steps comprising:

monitoring when data for a specified device is available for error correction code generation;

generating new error correction code in hardware for said data based on said indicated size of said data; and

correcting detected errors in software based on said generated new error correction code.

97. The machine-readable storage according to claim 96, comprising code for receiving a first indication of said specified device, a second indication of said data and a third indication of a size of said data, during said monitoring.

98. The machine-readable storage according to claim 96, comprising code for indicating when said generating of said new error correction code for a specified number of accesses for at least a portion of said data is complete.

99. The machine-readable storage according to claim 96, comprising code for enabling or disabling said error correction code generation.

100. The machine-readable storage according to claim 97, wherein said enabling and said disabling is accomplished via an enable signal.

101. The machine-readable storage according to claim 97, wherein said first indication comprises a device selection signal.

102. The machine-readable storage according to claim 97, wherein said second indication is a data ready signal.

103. The machine-readable storage according to claim 97, wherein said third indication of said size of said data is a data size signal.

104. The machine-readable storage according to claim 98, comprising code for counting said specified number of accesses.

105. The machine-readable storage according to claim 98, comprising code for controlling said specified number of accesses by a page size setting.

106. The machine-readable storage according to claim 96, comprising code for specifying a page counter that indicates bytes of said data that are processed.

107. The machine-readable storage according to claim 104, comprising code for generating an interrupt when said page counter indicates that all bytes are processed.

108. The machine-readable storage according to claim 96, comprising code for generating a signal that indicates when said generation of said new error correction code is complete.

109. The machine-readable storage according to claim 96, comprising code for determining whether data access for said data is a read access or a write access.

110. The machine-readable storage according to claim 109, comprising:

code for deactivating error code generation for said data; and

code for writing said newly generated error correction code to external memory, if said data access is a write operation.

111. The machine-readable storage according to claim 109, comprising:

code for deactivating error correction code generation for said data; and

code for reading newly generated error correction code and reading stored error correction code corresponding to read data, if said data access is a read operation.

112. The machine-readable storage according to claim 111, comprising code for checking integrity of said read data.

113. The machine-readable storage according to claim 112, comprising code for comparing said newly generated error correction code with a stored error correction code corresponding to said read data.

114. The machine-readable storage according to claim 113, comprising code for determining whether said newly generated error correction code matches said stored error correction code.

115. The machine-readable storage according to claim 114, comprising code for determining whether said error correction code is incorrect, if said newly generated error correction code does not match said stored error correction code.

116. The machine-readable storage according to claim 115, comprising code for determining whether an error is correctable, if said error correction code is not in error.

117. The machine-readable storage according to claim 116, comprising code for correcting said error, if said error is correctable.

118. The machine-readable storage according to claim 116, comprising code for reporting said error, if said error is not correctable.

119. A system for ensuring data integrity in a data processing system, the system comprising:

one or more circuits that monitors when data for a specified device is available for error correction code generation;

said one or more circuits generates new error correction code in hardware for said data based on said indicated size of said data; and

said one or more circuits corrects detected errors in software based on said generated new error correction code.

120. The system according to claim 119, wherein said one or more circuits receives a first indication of said specified device, a second indication of said data and a third indication of a size of said data, during said monitoring.

121. The system according to claim 119, wherein said one or more circuits indicates when said generating of said new error correction code for a specified number of accesses for at least a portion of said data is complete.

122. The system according to claim 119, wherein said one or more circuits enables or disables said error correction code generation.

123. The system according to claim 120, wherein said enabling and said disabling is accomplished via an enable signal.

124. The system according to claim 120, wherein said first indication comprises a device selection signal.

125. The system according to claim 120, wherein said second indication is a data ready signal.

126. The system according to claim 120, wherein said third indication of said size of said data is a data size signal.

127. The system according to claim 121, wherein said one or more circuits counts said specified number of accesses.

128. The system according to claim 121, wherein said one or more circuits controls said specified number of accesses by a page size setting.

129. The system according to claim 119, wherein said one or more circuits specifies a page counter that indicates bytes of said data that are processed.

130. The system according to claim 127, wherein said one or more circuits generates an interrupt when said page counter indicates that all bytes are processed.

131. The system according to claim 119, wherein said one or more circuits generates a signal that indicates when said generation of said new error correction code is complete.

132. The system according to claim 119, wherein said one or more circuits determines whether data access for said data is a read access or a write access.

133. The system according to claim 132, wherein said one or more circuits:

deactivates error code generation for said data; and

writes said newly generated error correction code to external memory, if said data access is a write operation.

134. The system according to claim 132, wherein said one or more circuits:

deactivates error correction code generation for said data; and

reads newly generated error correction code and reading stored error correction code corresponding to read data, if said data access is a read operation.

135. The system according to claim 134, wherein said one or more circuits checks integrity of said read data.

136. The system according to claim 135, wherein said one or more circuits compares said newly generated error correction code with a stored error correction code corresponding to said read data.

137. The system according to claim 136, wherein said one or more circuits determines whether said newly generated error correction code matches said stored error correction code.

138. The system according to claim 137, wherein said one or more circuits determines whether said error correction code is incorrect, if said newly generated error correction code does not match said stored error correction code.

139. The system according to claim 138, wherein said one or more circuits determines whether an error is correctable, if said error correction code is not in error.

140. The system according to claim 139, wherein said one or more circuits corrects said error, if said error is correctable.

141. The system according to claim 139, wherein said one or more circuits reports said error, if said error is not correctable.

142. A system for ensuring data integrity in a data processing system, the system comprising:

at least one processor that monitors when data for a specified device is available for error correction code generation;

said at least one processor generates new error correction code in hardware for said data based on said indicated size of said data; and

said at least one processor corrects detected errors in software based on said generated new error correction code.

143. The system according to claim 142, wherein said at least one processor receives a first indication of said specified device, a second indication of said data and a third indication of a size of said data, during said monitoring.

144. The system according to claim 142, wherein said at least one processor indicates when said generating of said new error correction code for a specified number of accesses for at least a portion of said data is complete.

145. The system according to claim 142, wherein said at least one processor enables or disables said error correction code generation.

146. The system according to claim 143, wherein said enabling and said disabling is accomplished via an enable signal.

147. The system according to claim 143, wherein said first indication comprises a device selection signal.

148. The system according to claim 143, wherein said second indication is a data ready signal.

149. The system according to claim 143, wherein said third indication of said size of said data is a data size signal.

150. The system according to claim 144, wherein said at least one processor counts said specified number of accesses.

151. The system according to claim 144, wherein said at least one processor controls said specified number of accesses by a page size setting.

152. The system according to claim 142, wherein said at least one processor specifies a page counter that indicates bytes of said data that are processed.

153. The system according to claim 150, wherein said at least one processor generates an interrupt when said page counter indicates that all bytes are processed.

154. The system according to claim 142, wherein said at least one processor generates a signal that indicates when said generation of said new error correction code is complete.

155. The system according to claim 142, wherein said at least one processor determines whether data access for said data is a read access or a write access.

156. The system according to claim 155, wherein said at least one processor:

deactivates error code generation for said data; and

writes said newly generated error correction code to external memory, if said data access is a write operation.

157. The system according to claim 155, wherein said at least one processor:

deactivates error correction code generation for said data; and

reads newly generated error correction code and reading stored error correction code corresponding to read data, if said data access is a read operation.

158. The system according to claim 157, wherein said at least one processor checks integrity of said read data.

159. The system according to claim 158, wherein said at least one processor compares said newly generated error correction code with a stored error correction code corresponding to said read data.

160. The system according to claim 159, wherein said at least one processor determines whether said newly generated error correction code matches said stored error correction code.

161. The system according to claim 160, wherein said at least one processor determines whether said error correction code is incorrect, if said newly generated error correction code does not match said stored error correction code.

162. The system according to claim 161, wherein said at least one processor determines whether an error is correctable, if said error correction code is not in error.

163. The system according to claim 162, wherein said at least one processor corrects said error, if said error is correctable.

164. The system according to claim 162, wherein said at least one processor reports said error, if said error is not correctable.