Design Structure and System for Identification of Defects on Circuits or Other Arrayed Products

• US 20080148201A1
• Filed: 01/04/2008
• Published: 06/19/2008
• Est. Priority Date: 06/10/2003
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lanzerotti, Mary, Yashchin, Emmanuel, Trapp, Brian, Takken, Asya, Landers, Christina
• Application Number:
  US11/969,294
• Publication Number:
  US 20080148201A1
• Time in Patent Office: Days
• US Class Current: 716/5
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A system and method is disclosed for assessing a probability of failure of operation of a semiconductor wafer. The method includes inputting risk factor data into a memory and inputting a plurality of wafers into a semiconductor fabrication manufacturing process. A subset of wafers is selected to obtain a sample population and at least one region of each wafer of the sample population is inspected. Circuit design data associated with each wafer of the sample population is obtained and one or more defects that present an increased risk to the operation of a particular wafer are identified. The identification is a function of the risk factor data, the inspecting step and the circuit design data. A probability of semiconductor wafer failure is calculated.

Claims

1-16. -16. (canceled)

17. An apparatus comprising:

a calculation module adapted to generate a risk map that associates quantitatively weighted risk factors with locations of design shapes across at least one layer of a device, wherein the design shapes are from circuit design data of the device;

a location module adapted to establish a list of measured defect locations as a function of the circuit design data; and

an evaluation module adapted to generate an output that identifies an inspection area of the at least one layer as a function of the quantitatively weighted risk factors applied to the list of measured defects.

18. The apparatus of claim 17, wherein the evaluation module is adapted to generate the output in real-time while the location module establishes the list of measured defects.

19. The apparatus of claim 17, wherein the risk factors are a function of a metal fraction of the design shapes.

20. The apparatus of claim 17, wherein at least one of the risk factors is a function of a critical area of the at least one layer.

21. The apparatus of claim 17, further comprising:

a review module, coupled to the evaluation module, the review module adapted to provide input to the evaluation module that includes review data that revises the list of measured defect locations to include at least one of defect type and defect size.

22. The apparatus of claim 17, wherein the evaluation module is provided data related to prior assessments of flaws.

23. An apparatus for assessing one or more flaws in a circuit comprising:

means for generating a risk map that associates quantitatively weighted risk factors with locations of design shapes across at least one layer of a device, wherein the design shapes are from circuit design data of the device;

means for establishing a list of measured defect locations as a function of the circuit design data; and

means for generating an output that identifies an inspection area of the at least one layer as a function of the quantitatively weighted risk factors applied to the list of measured defects.

25. The apparatus of claim 23, wherein at least one of the risk factors is a function of a critical area of the at least one layer.

24. (canceled)

26-34. -34. (canceled)

35. A medium tangibly embodying a computer program that is readable by a computer to perform actions directed toward assessing the probability of failure of a semiconductor chip due to at least one defect, the actions comprising:

generating a risk map that associates quantitatively weighted risk factors with locations of design shapes across at least one layer of a device, wherein the design shapes are from circuit design data of the device;

establishing a list of measured defect locations as a function of the circuit design data; and

generating an output that identifies an inspection area of the at least one layer as a function of the quantitatively weighted risk factors applied to the list of measured defects.

36. The medium of claim 35, wherein generating the output is in real-time with establishing the list of measured defects.

37. The medium of claim 35, wherein the risk factors are a function of a metal fraction of the design shapes.

38. The medium of claim 35, wherein at least one of the risk factors is a function of a critical area of the at least one layer.

39. The medium of claim 35, further comprising:

revising the list of measured defect locations to include at least one of defect type and defect size,

and wherein generating the output is a function of the quantitatively weighted risk factors applied to the revised list of measured defects.

40. A method comprising:

generating a risk map that associates quantitatively weighted risk factors with locations of design shapes across at least one layer of a device, wherein the design shapes are from circuit design data of the device;

establishing a list of measured defect locations as a function of the circuit design data; and

generating an output that identifies an inspection area of the at least one layer as a function of the quantitatively weighted risk factors applied to the list of measured defects.

41. The method of claim 40, wherein generating the output is in real-time with establishing the list of measured defects.

42. The method of claim 40, wherein the risk factors are a function of a metal fraction of the design shapes.

43. The method of claim 40, wherein at least one of the risk factors is a function of a critical area of the at least one layer.

44. The method of claim 40, further comprising:

revising the list of measured defect locations to include at least one of defect type and defect size,

and wherein generating the output is a function of the quantitatively weighted risk factors applied to the revised list of measured defects.

45. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

circuit design data that comprises design shapes for at least one layer of a device;

a risk map that associates quantitatively weighted risk factors with locations of the design shapes across the at least one layer of the device;

a list of measured defect locations as a function of the circuit design data; and

an inspection area of the at least one layer, the inspection area identified as a function of the quantitatively weighted risk factors applied to the list of measured defects.