METHOD OF PARTITIONING AN ALGORITHM BETWEEN HARDWARE AND SOFTWARE

• US 20080148227A1
• Filed: 12/14/2007
• Published: 06/19/2008
• Est. Priority Date: 05/17/2002
• Status: Active Grant

• Current Assignee: Pixel Velocity Incorporated
• Original Assignee: Pixel Velocity Incorporated
• Inventors: McCubbrey, David L.
• Granted Patent: US 8,230,374 B2
• Time in Patent Office: Days
• US Class Current: 717/110
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 8/456 Parallelism detection
• CPC Class Codes: H05K 1/144 Stacked arrangements of planar printed circuit boards

Abstract

A method of partitioning an algorithm between hardware and software includes accepting a user defined algorithm specified in a source code, identifying worker methods and feature extraction methods within the user defined algorithm, replacing worker methods in the source code with hardware logic, replacing feature extraction methods with a combination of hardware logic and software libraries that interface with the hardware logic, and outputting an FPGA programming specification of the hardware logic and interface libraries.

Claims

1. A method of partitioning an algorithm between hardware and software comprising:

accepting a user defined algorithm specified in a source code;

identifying worker methods and feature extraction methods within the user defined algorithm;

replacing worker methods in the source code with hardware logic;

replacing feature extraction methods with a combination of hardware logic and software libraries that interface with the hardware logic; and

outputting an FPGA programming specification of the hardware logic and interface libraries.

2. The method of claim 1, wherein the source code is specified in a high level programming language.

3. The method of claim 1, wherein the source code is specified in C++.

4. The method of claim 1, wherein the identifying step includes parsing the source code.

5. The method of claim 1, wherein the worker methods are image processing methods.

6. The method of claim 1, wherein the step of replacing worker methods includes stubbing out the source code that corresponds to the worker methods.

7. The method of claim 1, wherein the feature extraction methods output symbolic information.

8. The method of claim 1, wherein the feature extraction methods are methods selected from the group consisting of generating histograms of image pixel values, listing image coordinate/value pairs, counting pixels having a specific value, listing features, listing feature locations, listing maximum and minimum values, listing minimum and maximum value locations.

9. The method of claim 1, wherein the interface libraries are real-time embedded libraries.

10. The method of claim 9, wherein the real-time embedded libraries retrieve data from the hardware logic.

11. The method of claim 1, further comprising the step of testing the software program with an input data set.

12. The method of claim 10, wherein the input data set is collected under the same conditions as deployment.

13. The method of claim 12, wherein the input data set is collected using an embedded target machine.

14. The method of claim 1, wherein the FPGA programming specification is in a vendor specific low-level format.

15. The method of claim 1, wherein the FPGA programming specification is a hardware gate programming bitstream.