Transmitting and receiving circuit and semiconductor device including the same

• US 20080149738A1
• Filed: 12/20/2007
• Published: 06/26/2008
• Est. Priority Date: 12/26/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Fujita, Masashi, Shionoiri, Yutaka
• Granted Patent: US 8,036,604 B2
• Time in Patent Office: Days
• US Class Current: 235/492
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/327 Amplitude shift keying modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/245 with semiconductor devices only

Abstract

An object is to provide a circuit configuration with which the number of transistors can be reduced and power conversion efficiency can be prevented from being reduced, in a transmitting and receiving circuit. The transmitting and receiving circuit includes a voltage doubler rectifier circuit having N stages, each of which includes a capacitor, where N is a positive integer. The voltage doubler rectifier circuit having N stages is connected to a circuit having a modulation function. In the capacitor in any one of the N stages, one electrode of the one capacitor is connected to an input terminal of the transmitting and receiving circuit, and a node to which the other electrode of the one capacitor is connected is connected to a circuit having a demodulation function. Since the transmitting and receiving circuit can be formed of fewer transistors, it can be reduced in size. Since a reduction in power conversion efficiency can be prevented, a power supply potential can be efficiently generated.

Claims

1. A transmitting and receiving circuit comprising:

a voltage doubler rectifier circuit having N stages, each of which comprises a capacitor, where N is a positive integer;

a circuit having a modulation function connected to the voltage doubler rectifier circuit;

wherein the capacitor in one of N stages having one electrode connected to an input terminal of the transmitting and receiving circuit; and

the other electrode connected to a node connected to a circuit having a demodulation function.

2. The transmitting and receiving circuit according to claim 1, wherein each of the circuit having a modulation function and the circuit having a demodulation function comprises a plurality of diodes.

3. The transmitting and receiving circuit according to claim 2, wherein each of the plurality of diodes is configured with a diode-connected transistor.

4. The transmitting and receiving circuit according to claim 3, wherein the transistor is an n-channel transistor or a p-channel transistor.

5. The transmitting and receiving circuit according to claim 1, wherein the capacitor and a resistor are connected to an output terminal of the circuit having a demodulation function.

6. The transmitting and receiving circuit according to claim 5, wherein the capacitance of the capacitor is 1 to 10 pF and the resistance of the resistor is 10 to 100 kΩ

.

7. The transmitting and receiving circuit according to claim 1, wherein a diode is connected between the output terminal of the circuit having a demodulation function and an output terminal of the voltage doubler rectifier circuit having N stages.

8. The transmitting and receiving circuit according to claim 1, wherein a capacitor is connected to the output terminal of the voltage doubler rectifier circuit having N stages.

9. A semiconductor device comprising:

an antenna which receives a radio wave supplied externally;

a transmitting and receiving circuit connected to the antenna, and performing output, modulation, and demodulation of a DC voltage when a wireless signal received by the antenna is inputted;

a power supply circuit generating a power supply voltage from the DC voltage; and

a memory circuit and a control circuit to which a demodulated signal is inputted,

wherein the transmitting and receiving circuit comprises a voltage doubler rectifier circuit having N stages, each of which comprises a capacitor, where N is a positive integer;

wherein the voltage doubler rectifier circuit having N stages is connected to a circuit having a modulation function;

wherein the capacitor in one of N stages having one electrode connected to an input terminal of the transmitting and receiving circuit; and

the other electrode connected to a node connected to a circuit having a demodulation function.

10. The semiconductor device according to claim 9, wherein each of the circuit having a modulation function and the circuit having a demodulation function comprises a plurality of diodes.

11. The semiconductor device according to claim 10, wherein each of the plurality of diodes is configured with a diode-connected transistor.

12. The semiconductor device according to claim 11, wherein the transistor is an n-channel transistor or a p-channel transistor.

13. The semiconductor device according to claim 9, wherein the capacitor and a resistor are connected to an output terminal of the circuit having a demodulation function.

14. The semiconductor device according to claim 13, wherein the capacitance of the capacitor is 1 to 10 pF and the resistance of the resistor is 10 to 100 kΩ

.

15. The semiconductor device according to claim 9, wherein a diode is connected between the output terminal of the circuit having a demodulation function and an output terminal of the voltage doubler rectifier circuit having N stages.

16. The semiconductor device according to claim 9, wherein a capacitor is connected to the output terminal of the voltage doubler rectifier circuit having N stages.