III-Nitride Light Emitting Device with Reduced Strain Light Emitting Layer

• US 20080149942A1
• Filed: 12/22/2006
• Published: 06/26/2008
• Est. Priority Date: 12/22/2006
• Status: Active Grant

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Philips Lumileds Lighting Company LLC (Apollo Global Management, Inc.)
• Inventors: Krames, Michael R., Gardner, Nathan F., Romano, Linda T., David, Aurelien J. F., Yi, Sungsoo
• Granted Patent: US 7,663,148 B2
• Time in Patent Office: Days
• US Class Current: 257/79
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers

Abstract

In accordance with embodiments of the invention, strain is reduced in the light emitting layer of a III-nitride device by including a strain-relieved layer in the device. The surface on which the strain-relieved layer is grown is configured such that strain-relieved layer can expand laterally and at least partially relax. In some embodiments of the invention, the strain-relieved layer is grown over a textured semiconductor layer or a mask layer. In some embodiments of the invention, the strain-relieved layer is group of posts of semiconductor material.

Claims

1. A device comprising:

a III-nitride semiconductor structure comprising;

a light emitting layer disposed between an n-type region and a p-type region; and

a textured surface disposed within 1000 angstroms of the light emitting layer.

2. The device of claim 1 wherein the light emitting layer is adjacent to the textured surface.

3. The device of claim 1 wherein the textured surface is disposed within the n-type region.

4. The device of claim 1 wherein the textured surface comprises features lithographically formed on a III-nitride layer such that the features have a cross sectional profile resembling peaks separated by valleys.

5. The device of claim 4 wherein a largest lateral extent between two adjacent peaks is less than 200 nm.

6. The device of claim 1 wherein the textured layer comprises a layer of insulating material disposed within the semiconductor structure, wherein a plurality of openings are disposed in the insulating material.

7. The device of claim 6 wherein the insulating material comprises at least one nitride of silicon.

8. The device of claim 6 wherein a largest lateral extent of one of the openings is less than 200 nm.

9. The device of claim 6 wherein a largest lateral extent of one of the openings is less than 100 nm.

10. The device of claim 1 wherein:

the light emitting layer has bulk lattice constant a_bulk corresponding to a lattice constant of a free standing material of a same composition as the light emitting layer;

the light emitting layer has an in-plane lattice constant a_in-plane corresponding to a lattice constant of the light emitting layer as grown in the structure; and

(a_in-plane-a_bulk)/a_bulk is less than 1%.

11. The device of claim 1 wherein the light emitting layer has a thickness greater than 50 angstroms.

12. The device of claim 1 wherein the light emitting layer is doped with silicon to a dopant concentration between 1×

10¹⁸ cm<sup>−

3</sup> and 1×

10²⁰cm<sup>−

3</sup>.

13. The device of claim 1 further comprising:

contacts electrically connected to the n-type region and the p-type region; and

a cover disposed over the III-nitride semiconductor structure.

14. A device comprising:

a mask layer having a plurality of openings;

a III-nitride structure comprising;

a plurality of posts of semiconductor material corresponding to the openings in the mask layer, wherein the plurality of posts are separated by an insulating material, and wherein at least 90% of a cross section of the plurality of posts in a plane parallel to a surface of the mask layer is occupied by posts;

a light emitting layer disposed between an n-type region and a p-type region.

15. The device of claim 14 wherein the mask layer comprises silicon and nitrogen.

16. The device of claim 14 wherein each of the posts has a diameter less than 150 nm.

17. The device of claim 14 wherein the light emitting layer is disposed within the posts.

18. The device of claim 14 further comprising a planar layer of p-type semiconductor material disposed over the plurality of posts.

19. The device of claim 14 further comprising a planar layer of n-type semiconductor material disposed over the plurality of posts.

20. The device of claim 14 wherein the posts have a height between 50 nm and 3 μ

m.

21. The device of claim 14 wherein the insulating material is one of air, a resistive III-nitride material, and an oxide of silicon.

22. The device of claim 14 wherein the posts are truncated polyhedrons.

23. The device of claim 14 wherein the posts are polyhedrons.

24. The device of claim 14 wherein the light emitting layer is a conformal layer formed over the polyhedrons.

25. The device of claim 14 wherein:

the light emitting layer has bulk lattice constant a_bulk corresponding to a lattice constant of a free standing material of a same composition as the light emitting layer;

the light emitting layer has an in-plane lattice constant a_in-plane corresponding to a lattice constant of the light emitting layer as grown in the structure; and

(a_in-plane-a_bulk)/a_bulk is less than 1%.

26. The device of claim 14 wherein the light emitting layer has a thickness greater than 50 angstroms.

27. The device of claim 14 wherein the light emitting layer is doped with silicon to a dopant concentration between 1×

10¹⁸cm<sup>−

3</sup> and 1×

10²⁰cm<sup>−

3</sup>.

28. The device of claim 14 further comprising:

contacts electrically connected to the n-type region and the p-type region; and

a cover disposed over the III-nitride semiconductor structure.