Transistor having recess channel and fabricating method thereof

• US 20080150015A1
• Filed: 09/18/2007
• Published: 06/26/2008
• Est. Priority Date: 12/26/2006
• Status: Active Grant

• Current Assignee: SK Keyfoundry Incorporated
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Cho, Cheol-Ho
• Granted Patent: US 7,767,530 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A transistor includes a substrate including a trench, an insulation layer filled in a portion of the trench, the insulation layer having a greater thickness over an edge portion of a bottom surface of the trench than over a middle portion of the bottom surface of the trench, a gate insulation layer formed over inner sidewalls of the trench, the gate insulation layer having a thickness smaller than the insulation layer, and a gate electrode filled in the trench.

Claims

1. A transistor, comprising:

a substrate including a trench;

an insulation layer filled in a portion of the trench, the insulation layer having a greater thickness over an edge portion of a bottom surface of the trench than over a middle portion of the bottom surface of the trench;

a gate insulation layer formed over inner sidewalls of the trench, the gate insulation layer having a thickness smaller than the insulation layer; and

a gate electrode filled in the trench.

2. The transistor of claim 1, wherein the insulation layer comprises an oxide-based material.

3. The transistor of claim 1, wherein the insulation layer is formed to a thickness ranging from approximately 2,000 Å

to approximately 3,000 Å

.

4. The transistor of claim 1, wherein the substrate comprises:

a silicon substrate; and

an epitaxial layer formed over the silicon substrate.

5. The transistor of claim 4, wherein the trench is formed in the epitaxial layer.

6. The transistor of claim 1, wherein the trench has a depth ranging from approximately 1.2 μ

m to approximately 2.0 μ

m and a width ranging from approximately 0.38 μ

m to approximately 0.47 μ

m.

7. A transistor, comprising:

a substrate including a trench;

an insulation layer filled in a portion of the trench, the insulation layer having a V shape;

a gate insulation layer formed over inner sidewalls of the trench, the gate insulation layer having a thickness smaller than the insulation layer; and

a gate electrode filled in the trench.

8. The transistor of claim 7, wherein the insulation layer comprises an oxide-based material.

9. The transistor of claim 7, wherein the insulation layer is formed to a thickness ranging from approximately 2,000 Å

to approximately 3,000 Å

.

10. The transistor of claim 7, wherein the substrate comprises:

a silicon substrate; and

an epitaxial layer formed over the silicon substrate.

11. The transistor of claim 10, wherein the trench is formed in the epitaxial layer.

12. The transistor of claim 7, wherein the trench has a depth ranging from approximately 1.2 μ

m to approximately 2.0 μ

m and a width ranging from approximately 0.38 μ

m to approximately 0.47 μ

m.

13. A method for fabricating a transistor, comprising:

forming a trench in a substrate;

forming a polysilicon layer over the substrate and filled in the trench;

etching the polysilicon layer in a manner that a portion of the polysilicon layer having a greater thickness over an edge portion of a bottom surface of the trench than over a middle portion of the bottom surface of the trench remains in the trench;

oxidizing the remaining portion of the polysilicon layer to form an insulation layer over the bottom surface of the trench and forming a gate insulation layer over inner sidewalls of the trench to a smaller thickness than the insulation layer at substantially the same time; and

forming a gate electrode over the insulation layer and filled in the trench.

14. The method of claim 13, wherein forming the polysilicon layer comprises forming an undoped polysilicon layer which is not doped with impurity ions.

15. The method of claim 13, wherein forming the polysilicon layer comprises forming the polysilicon layer in a manner that a depression is generated over a middle portion of the trench.

16. The method of claim 13, wherein etching the polysilicon layer in the manner that the portion of the polysilicon layer remains in the trench comprises performing an etch-back process.

17. The method of claim 16, wherein the etch-back process comprises performing the etch-back process at a pressure ranging from approximately 0.4 Pa to approximately 0.6 Pa at a temperature ranging from approximately 500°

C. to approximately 800°

C. using sulfur hexafluoride (SF₆) gas.

18. The method of claim 13, wherein oxidizing the remaining portion of the polysilicon layer to form the insulation layer and forming the gate insulation layer over the inner sidewalls of the trench comprise using nitrogen (N₂) gas and oxygen (O₂) gas mixed at a ratio of approximately 20:

4 (SLPM) at a temperature ranging from approximately 1,000°

C. to approximately 1,200°

C.

19. The method of claim 13, further comprising, after forming the trench:

oxidizing inner surfaces of the trench to form a first sacrificial oxide layer;

removing the first sacrificial oxide layer; and

forming a second sacrificial oxide layer.

20. The method of claim 19, further comprising, after etching the polysilicon layer in the manner that the portion of the polysilicon layer remains in the trench, removing the second sacrificial oxide layer.

21. The method of claim 13, wherein the insulation layer has a thickness ranging from approximately 2,000 Å

to approximately 3,000 Å

.

22. The method of claim 13, wherein the substrate comprises:

a silicon substrate; and

an epitaxial layer formed over the silicon substrate.