Semiconductor Device and Method of Manufacturing a Semiconductor Device

• US 20080150024A1
• Filed: 02/10/2005
• Published: 06/26/2008
• Est. Priority Date: 02/19/2004
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV), Waters Investments Limited (Waters Corporation)
• Original Assignee: Koninklijke Philips N.V.
• Inventors: Doornbos, Gerben, Van Dal, Marcus Johannes Henricus, Surdeanu, Radu Catalin
• Application Number:
  US10/597,996
• Publication Number:
  US 20080150024A1
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

This invention relates to a semiconductor device (105) and a method of manufacturing this device. A preferred embodiment of the invention is a semiconductor device (105) comprising a silicon semiconductor substrate (110), an oxide layer (115) and an active layer (120). In the active layer, insulating areas (125) and an active area (127) have been formed. The active area (127) comprises a source (180), a drain (182) and a body (168). The source (180) and drain (182) also comprise source and drain extensions (184, 186). The active layer (120) is provided with a gate (170). On both sides of the gate (170), L-shaped side wall spacers are located. The source (180) and drain (182) also comprise silicide regions (190, 192). A characteristic of these regions is that they have extensions (194, 196) located under the side wall spacers (136, 138). These extensions (194, 196) strongly reduce the series resistance of the source (194) and drain (196), which significantly improves the performance of the semiconductor device (105).

Claims

1. A semiconductor device (105, 205) comprising a silicon-containing semiconductor body (110, 210) with a surface (126, 226), which semiconductor body (110, 210) is provided, near the surface thereof (126, 226), with a transistor comprising:

a gate (170, 270) situated at the surface (126, 226) and having a side wall spacer (136, 138, 236) on either side of the gate, and further comprising, on either side of the gate (170, 270), a diffusion region (180, 182, 280) formed in the semiconductor body (110, 210), at least one diffusion region (180, 182, 280) being provided at the surface (126, 226) of the semiconductor body (110, 210) with a silicide (190, 192), characterized in that the silicide (190, 192) extends along the surface (126, 226) of the semiconductor body (110, 210) and continues for more than 10 nm under the side wall spacer (136, 138, 236).

2. A semiconductor device (105, 205) as claimed in claim 1, characterized in that the silicide (190, 192) contains a metal which, in the silicide formed, has a higher diffusion rate than silicon.

3. A semiconductor device (105, 205) as claimed in claim 2, characterized in that the metal (118) is selected from the group comprising nickel (Ni), platinum (Pt) and palladium (Pd) and alloys of these metals.

4. A semiconductor device (105) as claimed in claim 1, characterized in that the side wall spacer (136, 138) is L-shaped and comprises a first portion, which borders on the gate (170) and extends substantially perpendicularly with respect to the surface (126) of the semiconductor body (110), and a second portion which extends along the surface (126) of the semiconductor body (110).

5. A semiconductor device (105) as claimed in claim 4, characterized in that the second portion of the L-shaped side wall spacer (136, 138) has a thickness (D2), measured in a direction perpendicular to the surface (126) of the semiconductor body (110), of maximally 40 nm.

6. A semiconductor device (105, 205) as claimed in claim 1, characterized in that an insulating layer (115, 215) extends in the semiconductor body (110, 210) in a direction parallel to the surface (126, 226) of the semiconductor body (110, 210).

7. A semiconductor device (105) as claimed in claim 1, characterized in that the semiconductor body (110) comprises a germanium component.

8. A semiconductor device (105) as claimed in claim 1, characterized in that the semiconductor body (110) comprises a strained-silicon layer.

9. A method of manufacturing a semiconductor device (105, 205) as claimed in claim 1, comprising the steps of:

providing a silicon-containing semiconductor body (110, 210) having a surface (126, 226) which is provided with a gate (170, 270);

forming a side wall spacer (136, 138, 236) on either side of the gate (170, 270);

forming a diffusion region (180, 182, 280) in the semiconductor body (110, 210) on either side of the gate (170, 270);

carrying out an amorphization implantation (116, 216) to render the silicon of the semiconductor body (110, 210) amorphous at the surface (126, 226) of the diffusion regions (180, 182, 280), and

converting the silicon (189, 191, 289) that has been rendered amorphous into a silicide via interaction with a metal (118),

characterized in that

for the conversion of the silicon (189, 191, 289) that has been rendered amorphous into a silicide (190) use is made of a metal (118) which has a higher diffusion rate in the silicide (190) formed than silicon.

10. A method as claimed in claim 9, characterized in that the metal (118) is selected from the group comprising nickel (Ni), Platinum (Pt) and palladium (Pd), and alloys of these metals.

11. A method as claimed in claim 9, characterized in that the amorphization implantation angle (H1, H2) is larger than 0 degrees.

12. A method as claimed in claim 9, characterized in that the side wall spacer (136, 138) is formed so as to be L-shaped, comprising a first portion, which borders on the gate (170) and extends substantially perpendicularly with respect to the surface (126) of the semiconductor body (110), and a second portion, which extends along the surface (126) of the semiconductor body (110).

13. A method as claimed in claim 12, characterized in that the second portion of the L-shaped side wall spacer (136, 138) is formed with a thickness (D2), measured in a direction perpendicular to the surface (126) of the semiconductor body (110), of maximally 40 nm.