Semiconductor apparatus and manufacturing method thereof

• US 20080150032A1
• Filed: 02/13/2008
• Published: 06/26/2008
• Est. Priority Date: 08/18/2005
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Tanaka, Takuji
• Granted Patent: US 8,026,577 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor apparatus according to the present invention includes a first well-region and a second well-region in a semiconductor substrate, and a plurality of transistors formed to the second well-region. Further, the semiconductor apparatus includes a through-hole region that is formed so as to pierce through the first well-region and enables the second well-region to be electrically conductive to the semiconductor substrate on the bottom of the second well. Furthermore, in the semiconductor apparatus, the border of the through-hole region is arranged between the transistors, and is also arranged to be planarity apart from the transistor.

Claims

1. A semiconductor apparatus comprising:

a first-conductive-type semiconductor substrate;

a second-conductive-type first well-region formed in a surface layer of the semiconductor substrate;

a first-conductive-type second well-region that is formed in the surface layer of the semiconductor substrate and is formed in contact with the first well-region;

a plurality of transistors formed in the second well-region; and

a through-hole region that is formed so as to pierce through the first well-region, and enables the second well-region to be electrically conductive to the semiconductor substrate on the bottom of the second well-region,

wherein the border of the through-hole region is arranged between the transistors, and is arranged to be planarity apart from the transistor.

3. The semiconductor apparatus according to claim 1, wherein the transistors are an MOS transistor.

5. The semiconductor apparatus according to claim 1, wherein the first well-region comprises:

a first impurity-region includes the second-conductive-type impurity that is formed in the surface layer of the semiconductor substrate; and

a second impurity-region having the second-conductive-type impurity formed from the bottom of the second well-region toward the inside of the semiconductor substrate by another step of the first impurity-region.

7. The semiconductor apparatus according to claim 1, wherein the transistor is planarity apart from the border of the through-hole region so that the impurity concentration of impurity injected for forming the through-hole region on the surface of the second well-region is reduced under predetermined impurity concentration, as compared with the impurity concentration at the border of the through-hole region.

2. A semiconductor apparatus comprising:

a semiconductor substrate having a first conductive type;

a first well-region of a second conductive type that is formed in a surface layer of the semiconductor substrate;

a first-conductive-type second well-region that is formed in the surface layer of the semiconductor substrate in contact with the first well-region;

a transistor that is formed in the second well-region; and

a through-hole region that is formed so as to pierce through the first well-region, and enables the second well-region to be electrically conductive to the semiconductor substrate on the bottom of the second well-region,

wherein the transistor is arranged in the through-hole region, and the border of the through-hole region is arranged to be planarity apart from the transistor.

4. The semiconductor apparatus according to claim 2, wherein the transistors are an MOS transistor.

6. The semiconductor apparatus according to claim 2, wherein the first well-region comprises:

a first impurity-region includes the second-conductive-type impurity that is formed in the surface layer of the semiconductor substrate; and

a second impurity-region having the second-conductive-type impurity formed from the bottom of the second well-region toward the inside of the semiconductor substrate by another step of the first impurity-region.

8. The semiconductor apparatus according to claim 2, wherein the transistor is planarity apart from the border of the through-hole region so that the impurity concentration of impurity injected for forming the through-hole region is reduced under predetermined impurity concentration, as compared with the impurity concentration at the border of the through-hole region.

9. A manufacturing method of a semiconductor apparatus comprising:

preparing a first-conductive-type semiconductor substrate;

injecting a second-conductive-type impurity to a first well-region of the semiconductor substrate;

injecting a first-conductive-type impurity to a second well-region in contact with the bottom of the first well-region,

wherein the second well-region has a through-hole region having the same potential as that of the semiconductor substrate.

10. The manufacturing method of the semiconductor apparatus according to claim 9, further comprising:

injecting a first-conductive-type impurity to the through-hole region.

11. A manufacturing method of a semiconductor apparatus comprising:

forming a first-conductive-type first well-region in the semiconductor substrate including a surface of a first-conductive-type semiconductor substrate;

forming a first-conductive-type second well-region in the first well-region in the semiconductor substrate including a surface of the semiconductor substrate;

forming a plurality of transistors in the first well-region; and

forming a through-hole region that enables the second well-region to be electrically conductive to the semiconductor substrate, formed to be pierced through the first well-region, on the bottom of the second well-region,

wherein the border of the through-hole region is arranged between the transistors, and is arranged to be planarity apart from the transistor.