Transistor Driver Circuit of Power Converter

• US 20080150503A1
• Filed: 12/21/2006
• Published: 06/26/2008
• Est. Priority Date: 12/21/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: System General Corporation (ON Semiconductor Corporation)
• Inventors: Tsao, Feng-Cheng, Wang, Jesse R., Yang, Ta-Yung, Li, Chuh-Ching
• Granted Patent: US 7,471,121 B2
• Time in Patent Office: Days
• US Class Current: 323/282
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 3/335 using semiconductor devices only
• CPC Class Codes: H03K 17/08122 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/22 Modifications for ensuring a predetermined initial state when the supply voltage has been applied bi-stable generators H03K3/12
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor

Abstract

A transistor drive circuit of a power converter is developed for operating in wide voltage range. It includes an N-type high-side transistor, a P-type high-side transistor and an N-type low-side transistor. A voltage clamp device is connected to the gate of the N-type high-side transistor to limit the maximum output voltage. A detection circuit is coupled to detect the supply voltage of the transistor drive circuit to generate a disable signal in response to the voltage level of the supply voltage. The disable signal is coupled to disable the P-type high-side transistor once the voltage level of the supply voltage is higher than a threshold voltage.

Claims

1. A transistor drive circuit of a power converter, comprising:

an input terminal to receive a supply voltage;

an output terminal to output a switching signal for driving a transistor of the power converter;

an N-type high-side transistor having a drain terminal coupled to the input terminal, a source terminal of the N-type high-side transistor coupled to the output terminal;

a P-type high-side transistor having a source terminal coupled to the input terminal, a drain terminal of the P-type high-side transistor coupled to the output terminal;

an N-type low-side transistor having a drain terminal coupled to the output terminal, a source terminal of the N-type low-side transistor coupled to a ground;

a first control circuit coupled to control the gate terminal of the N-type high-side transistor and the gate terminal of the P-type high-side transistor; and

a second control circuit coupled to control the gate terminal of the N-type low-side transistor.

2. The transistor drive circuit as claimed in claim 1, further comprising:

a detection circuit coupled to the supply voltage to generate a disable signal in response to the voltage level of the supply voltage,

wherein the disable signal is transmitted to the first control circuit to disable the P-type high-side transistor once the voltage level of the supply voltage is higher than a threshold voltage.

3. The transistor drive circuit as claimed in claim 1, further comprising a voltage clamp device coupled to the gate terminal of the N-type high-side transistor to clamp the maximum output voltage of the switching signal.

4. The transistor drive circuit as claimed in claim 1, wherein the first control circuit and the second control circuit are coupled to receive a control signal for generating the switching signal;

the first control circuit and the second control circuit are used to protect the N-type high-side transistor and the N-type low-side transistor from cross-conduction.

5. The transistor drive circuit as claimed in claim 1, wherein the first control circuit and the second control circuit are further used to protect the P-type high-side transistor and the N-type low-side transistor from cross-conduction.

6. A transistor drive circuit for driving a switching transistor of a power converter, comprising:

an input terminal to receive a supply voltage;

an output terminal to output a switching signal for driving the switching transistor;

a first type-I transistor coupled between the input terminal and the output terminal;

a first type-II transistor coupled between the input terminal and the output terminal;

a second type-I transistor coupled between the output terminal and a ground; and

a control circuitry to control the type-I and type-II transistors in response to a control signal.

7. The transistor drive circuit as claimed in claim 6, wherein the first and second type-I transistors are N-type transistors, and the first type-II transistor is a P-type transistor.

8. The transistor drive circuit as claimed in claim 6, wherein the control circuitry comprises:

a first control circuit coupled to control the first type-I and type-II transistors; and

a second control circuit coupled to control the second type-I transistor,

wherein the first control circuit and the second control circuit are used to protect the first type-I transistor and the second type-I transistor from cross-conduction; and

the first control circuit and the second control circuit are further used to protect the first type-II transistor and the second type-I transistor from cross-conduction.

9. The transistor drive circuit as claimed in claim 8, wherein the control circuitry further comprising a detection circuit coupled to the supply voltage to generate a disable signal in response to the voltage level of the supply voltage;

and the disable signal is transmitted to the first control circuit to disable the first type-II transistor once the voltage level of the supply voltage is higher than a threshold voltage.

10. The transistor drive circuit as claimed in claim 9, wherein the first control circuit comprises:

an inverter to invert a signal used for controlling the second type-I transistor;

an AND gate for receiving the control signal and an output of the inverter and outputting a signal to control the first type-I transistor; and

an NAND gate for outputting a signal to control the first type-II transistor in accordance with the disable signal and an output of the AND gate.

11. The transistor drive circuit as claimed in claim 8, wherein the second control circuit comprises:

a first inverter to invert a signal used for controlling the first type-I transistor to generate a first signal; and

an AND gate for outputting a signal to control the second type-II transistor in accordance with the control signal and the first signal.

12. The transistor drive circuit as claimed in claim 6, further comprising a voltage clamp device coupled to the gate terminal of the first type-I transistor to clamp the maximum output voltage of the switching signal.