Method and Circuit Arrangement for Verifying Electrical Contacts Between a First Output Pin of a First Power Switch of a Power Switch Device and an External Node and a Second Ouput Pin of a Second Power Switch of Said Power Switch Device and Said Node

• US 20080150539A1
• Filed: 11/25/2005
• Published: 06/26/2008
• Est. Priority Date: 02/01/2005
• Status: Active Grant

• Current Assignee: Vitesco Technologies GmbH (Continental AG)
• Original Assignee: Siemens AG
• Inventors: Arndt, Bastian, Wolfarth, Gunther
• Granted Patent: US 7,719,286 B2
• Time in Patent Office: Days
• US Class Current: 324/415
• CPC Class Codes: G01R 19/16538 in AC or DC supplies G01R19/16519 and G01R19/16528 take precedence
• CPC Class Codes: H03K 17/122 in field-effect transistor switches

Abstract

A first voltage, which is dropped out onto a pull-down resistor that is coupled to a first power circuit breaker, is compared to an adjustable first reference voltage in order to determine a first comparative value. A second voltage, which is dropped out onto the pull-up resistor that is coupled to the second power circuit breaker, is compared to an adjustable second reference voltage in order to determine a second comparative value. Determination then occurs according to the first comparative value and second comparative value as to whether the first output pin of the first power circuit breaker and the second output switch of the second power circuit breaker are contacted to each other. The first output pin and second output pin are connected to one another by way of a node outside the power circuit breaker.

Claims

1-8. -8. (canceled)

9. A method for verifying electrical contacts between a first output pin of a first power switch of a power switch device and an external node and between a second output pin of a second power switch of the power switch device and the node, comprising:

(a) coupling the first power switch to a pull-down resistor and coupling the second power switch to a pull-up resistor;

(b) connecting the first output pin and the second output pin to each other via the external node disposed outside of the power switch device;

(c) comparing a first voltage present between the first output pin and ground with an adjustable first reference voltage for determining a first comparative value;

(d) comparing a second voltage present between the second output pin and ground with an adjustable second reference voltage for determining a second comparative value; and

(e) concluding, in dependence on the first comparative value and the second comparative value, whether the first output pin of the first power switch and the second output pin of the second power switch of the power switch device are contacted to the external node via the contacts.

10. The method according to claim 9, wherein during the coupling in method step the pullup resistor and the pulldown resistor are interconnected in such a way that they embody a voltage divider between a test voltage and ground.

11. The method according to claim 10, wherein the pull-up resistor and the pull-down resistor have mutually identical resistance values.

12. The method according to claim 10, which comprises setting the first reference voltage to less than a one-half test voltage, and setting the second reference voltage greater than the one-half test voltage.

13. The method according to claim 12, which comprises setting the first comparative value to a positive logic signal level if the first voltage is greater than the first reference voltage, or setting the first comparative value to a negative logic signal level if the first voltage is less than the first reference voltage.

14. The method according to claim 13, wherein method step further comprises concluding that the contact between at least one of the first output pin and the first power switch or the contact between the second output pin and the second power switch has been interrupted if the first comparative value is set to a negative logic signal level and the second comparative value is set to a positive logic signal level.

15. The method according to claim 12, which comprises setting the second comparative value to a positive logic signal level if the second voltage is greater than the second reference voltage or setting the second comparative value to a negative logic signal level if the second voltage is less than the second reference voltage.

16. The method according to claim 15, wherein method step further comprises concluding that the contact between at least one of the first output pin and the first power switch or the contact between the second output pin and the second power switch has been interrupted if the first comparative value is set to a negative logic signal level and the second comparative value is set to a positive logic signal level.

17. The method according to claim 12, which comprises:

setting the first comparative value to a positive logic signal level if the first voltage is greater than the first reference voltage, or setting the first comparative value to a negative logic signal level if the first voltage is less than the first reference voltage; and

setting the second comparative value to a positive logic signal level if the second voltage is greater than the second reference voltage or setting the second comparative value to a negative logic signal level if the second voltage is less than the second reference voltage.

18. The method according to claim 17, wherein method step further comprises concluding that the contact between at least one of the first output pin and the first power switch or the contact between the second output pin and the second power switch has been interrupted if the first comparative value is set to a negative logic signal level and the second comparative value is set to a positive logic signal level.

19. A circuit configuration, comprising:

a power switch device including;

a first power switch connected to a first output pin;

a second power switch connected to a second output pin;

a node connected between said first output pin and said second output pin and disposed outside said power switch device; and

a diagnostic circuit coupled to said first and second power switches and configured to perform the method according to claim 9.