METHOD TO REDUCE POWER IN ACTIVE SHIELD CIRCUITS THAT USE COMPLEMENTARY TRACES

• US 20080150574A1
• Filed: 02/07/2008
• Published: 06/26/2008
• Est. Priority Date: 12/26/2006
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Ziomek, Jason
• Granted Patent: US 7,622,944 B2
• Time in Patent Office: Days
• US Class Current: 326/8
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption

Abstract

The present invention provides a method and apparatus for securing an integrated circuit. A pair of conductive security traces are arranged on an integrated circuit. Driver means provide complementary HIGH and LOW voltage levels to a respective first end of each of the conductive security traces. A first switch means temporarily interrupts the driver means and isolates the pair of conductive security traces. A second switch means temporarily connects the first ends of the isolated pair of conductive security traces to each other so that both conductive traces are at the same voltage. The voltage at the first end of one of the security traces at the LOW voltage is then boosted to one-half of the HIGH voltage level (VDD/2) by the HIGH (VDD) voltage level at the first end of the other security trace. First and second comparators are provided, each of which compares voltages on their respective first ends of the pair of conductive security traces with voltages on a respective second end of the pair of conductive security traces. Means are provided for logically combining the output signals of the first and second comparators.

Claims

1. An integrated circuit security apparatus, comprising:

a pair of conductive security traces configured to be arranged on an integrated circuit;

a driver means controlled by a clock signal for providing complementary HIGH and LOW voltage levels to respective first ends of the pair of conductive security traces; and

a first switching means for selectively coupling and decoupling the driver means to and from the ends of the pair of conductive security traces.

2. The integrated circuit security apparatus of claim 1, further comprising a second switching means for temporarily coupling the respective first ends of the pair of conductive security traces to one another such that both conductive traces are at a substantially equivalent voltage.

3. The integrated circuit security apparatus of claim 2 wherein the second switching means includes a bi-directional transmission gate.

4. The integrated circuit security apparatus of claim 1 wherein a LOW voltage level at the first end of one of the security traces is boosted to an intermediate voltage level between the complementary HIGH and LOW voltage levels by a HIGH voltage level at the first end of the other security trace thereby reducing power required from the driver means.

5. The integrated circuit security apparatus of claim 1 further comprising:

a first comparator and a second comparator configured to compare voltages on the respective first ends of the pair of conductive security traces with voltages on respective second ends of the pair of conductive security traces; and

a logic means for logically combining output signals of the first and second comparators.

6. The integrated circuit security apparatus of claim 1 wherein the pair of conductive security traces is configured to cancel induction of any voltages in proximate circuitry.

7. The integrated circuit security apparatus of claim 1 wherein the driver means and the first switching means include tri-state line drivers configured to produce complementary output signals.

8. An integrated circuit security apparatus, comprising:

a first conductive security trace and a second conductive security trace formed substantially parallel to one another as part of an integrated circuit;

a first driver circuit configured to produce a first driver output signal to a first end of the first security trace;

a second driver circuit configured to produce a second driver output signal to a first end of the second security trace; and

a first switching circuit configured to decouple respective output terminals of the first and second driver circuits from the first ends of the first and second security traces during signal transitions of the first and second driver output signals.

9. The integrated circuit security apparatus of claim 8 wherein:

the first driver circuit is further configured to be driven by a clock signal and has an output terminal that produces the first driver output signals alternately at a HIGH voltage level and a LOW voltage level; and

the second driver circuit is further configured to driven by the clock signal and has an output terminal that produces the second driver output signals which are complements of the first driver output signals.

10. The integrated circuit security apparatus of claim 8 further comprising a second switching circuit configured to couple the first ends of the first and the second security traces to one another during the signal transitions of the first and second driver circuits.

11. The integrated circuit security apparatus of claim 10 wherein the second switching circuit includes a transmission gate.

12. The integrated circuit security apparatus of claim 8 wherein a zero voltage level at the first end of one of the security traces is configured to be boosted to an intermediate voltage level between complementary HIGH and LOW voltage levels by a HIGH voltage level at the first end of the other security trace, thereby reducing a power level required from the first and second driver circuits to drive their respective output terminals from the LOW voltage level to the HIGH voltage level.

13. The integrated circuit security apparatus of claim 8 further comprising:

a first comparator and a second comparator configured to compare the respective first and second driver output signals with signals at respective second ends of the first and second conductive security traces; and

a logic circuit configured to combine output signals of the first and the second comparators.

14. The integrated circuit security apparatus of claim 8 wherein the first and the second conductive security traces are configured to cancel induction of any voltages in proximate circuitry.

15. The integrated circuit security apparatus of claim 8 wherein the first and second driver circuits and the first switching circuit each include tri-state line drivers configured to produce complementary output signals.

16. A method of securing an integrated circuit, comprising:

applying a first signal to a first end of a first conductive security trace;

applying a second signal that is complementary to the first signal to a first end of a second conductive trace;

temporarily isolating the respective first ends of the conductive security traces;

temporarily coupling the first ends of the isolated conductive security traces to one another; and

comparing voltages on the respective first ends of the conductive security traces with voltages on second ends of the conductive security traces.

17. The method of claim 16 further comprising temporarily coupling the first ends of the isolated conductive security traces to one another such that both conductive traces are at an average voltage of the HIGH and LOW voltages so that a voltage at the first end of one of the security traces at a LOW voltage level is boosted by the HIGH voltage level at the first end of the other security trace thereby reducing power required from a driver circuit to drive its output terminal to the HIGH voltage level.

18. The method of claim 16 further comprising logically combining output signals resulting from comparing voltages.

19. The method of claim 16 including arranging the first and the second conductive security traces to substantially cancel induction of any voltages in proximate circuitry.