Signal processing circuit, low-voltage signal generator and image display incorporating the same

• US 20080150924A1
• Filed: 02/21/2008
• Published: 06/26/2008
• Est. Priority Date: 05/18/2001
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Kubota, Yasushi, Washio, Hajime, Brownlow, Michael James, Cairns, Graham Andrew, Yamashita, Hidehiko
• Granted Patent: US 7,978,169 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.

Claims

1. A signal processing circuit comprising:

a first logic operation circuit which performs a logic operation using a high-amplitude logic signal;

a transmission system having a load capacitance; and

a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system.

2. The signal processing circuit as set forth in claim 1, wherein at least the first logic operation circuit is constituted by a silicon thin film transistor made of polysilicon.

3. The signal processing circuit as set forth in claim 1, further comprising a second logic operation circuit which is connected to the transmission system to perform a logic operation using the low-amplitude logic signal fed from the step-down level shifter through the transmission system.

4. The signal processing circuit as set forth in claim 1, further comprising:

a step-up level shifter which transforms an incoming low-amplitude logic signal from the transmission system to a high-amplitude logic signal having a higher amplitude than the low-amplitude logic signal for output; and

a second logic operation circuit which performs a logic operation using the incoming high-amplitude logic signal from the step-up level shifter.

5. The signal processing circuit as set forth in claim 4, wherein at least the second logic operation circuit is constituted by a silicon thin film transistor made of polysilicon.

6. A low-voltage signal generator provided in a signal processing circuit including:

a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; and

a transmission system having a load capacitance,

wherein the low-voltage signal generator transforms a high-amplitude logic signal to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal.

7. The low-voltage signal generator as set forth in claim 6, provided between an output end of the first logic operation circuit and the transmission system.

8. The low-voltage signal generator as set forth in claim 6, comprising transistors forming a gate circuit, wherein:

each transistor belongs to either a low level output group or a high level output group;

each transistor belonging to the low level output group is fed at a gate thereof with the high-amplitude logic signal and at an input end thereof with any one of a low-amplitude logic signal which remains at a low level throughout a period in which the high-amplitude logic signal is applied to the gate, a low level potential from a low level source for use to produce the low-amplitude logic signal, and a low level potential from a high level source for use to produce the high-amplitude logic signal, and outputs a low level potential of a low-amplitude logic signal through an output end thereof; and

each transistor belonging to the high level output group is fed at a gate thereof with the high-amplitude logic signal and at an input end thereof with either one of a low-amplitude logic signal which remains at a high level throughout the period and a high level potential from the low level source, and outputs a high level potential of a low-amplitude logic signal through an output end thereof.

9. The low-voltage signal generator as set forth in claim 8, wherein:

the signal processing circuit is used in an image display including pixels arranged in a matrix, data signal lines each provided for a different column of pixels, scan signal lines each provided for a different row of pixels, a data signal line drive circuit driving the data signal lines, and a scan signal line drive circuit driving the scan signal lines;

the low-amplitude logic signal which remains at a low level throughout the period is a start pulse signal representing when the data signal line drive circuit starts to operate; and

the low-amplitude logic signal which remains at a high level throughout the period is an inverse signal of the start pulse signal.

10. The low-voltage signal generator as set forth in the claim 8, wherein each transistor outputs the low-amplitude logic signal and an inverse signal thereof.

11. The low-voltage signal generator as set forth in the claim 6, constituted by a silicon thin film transistor made of polysilicon.

12. An image display, comprising:

pixels arranged in a matrix;

data signal lines each provided for a different column of pixels;

scan signal lines each provided for a different row of pixels;

a data signal line drive circuit driving the data signal lines; and

a scan signal line drive circuit driving the scan signal lines,

wherein

either one, or both, of the data signal line drive circuit and the scan signal line drive circuit include(s);

a first logic operation circuit which performs a logic operation using a high-amplitude logic signal;

a transmission system having a load capacitance; and

a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system.

13. The image display as set forth in claim 12, further comprising:

a second logic operation circuit which is connected to the transmission system to perform a logic operation using the low-amplitude logic signal fed from the step-down level shifter through the transmission system.

14. The image display as set forth in claim 12, further comprising:

a step-up level shifter which transforms an incoming low-amplitude logic signal from the transmission system to a high-amplitude logic signal having a higher amplitude than the low-amplitude logic signal for output; and

a second logic operation circuit which performs a logic operation using the incoming high-amplitude logic signal from the step-up level shifter.

15. The image display as set forth in claim 14, wherein

the first logic operation circuit is a clock frequency dividing circuit for dividing a clock signal in terms of frequency,

the second logic operation circuits are shift registers connected in series, and

the shift registers are connected to the step-up level shifters respectively.

16. The image display as set forth in claim 14, wherein

the first logic operation circuit is an inverse clock signal circuit which produces an inverse clock signal from a clock signal,

the second logic operation circuits are shift registers connected in series, and

the shift registers are connected to the step-up level shifters respectively.

17. The image display as set forth in claim 14, wherein

the data signal line drive circuit includes the step-down level shifter which is the low-voltage signal generator,

the first logic operation circuit is a circuit in which shift registers are connected in series and is a first shift register circuit which is a circuit determining a timing to sample digital data, and

the second logic operation circuit is a circuit in which shift registers are connected in series and is a second shift register circuit which is a circuit determining a timing to output to the data signal lines.

18. The image display as set forth in claim 12, wherein at least the first logic operation circuit is constituted by a silicon thin film transistor made of polysilicon.