8-T SRAM cell circuit, system and method for low leakage current

• US 20080151605A1
• Filed: 07/06/2007
• Published: 06/26/2008
• Est. Priority Date: 07/06/2006
• Status: Active Grant

• Current Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Inventors: Goel, Ankur
• Granted Patent: US 7,619,916 B2
• Time in Patent Office: Days
• US Class Current: 365/156
• CPC Class Codes: G11C 11/412 using field-effect transistors only

Abstract

An SRAM cell has reduced gate and sub-threshold leakage currents. The SRAM cell is designed to include eight operatively coupled transistors to reduce leakage currents irrespective of data stored in the SRAM cell. The transistors lower the effective supply voltage at different nodes, when either bit ‘0’ or ‘1’ is stored in the SRAM cell. The reduced effective supply voltage is passed to other coupled transistors for minimizing leakages. The SRAM cell operates in an active mode and dissipates no dynamic power during active mode to inactive mode transition and vice-versa operations. The SRAM cell is also capable of reducing bit line leakage currents under suitable conditions.

Claims

1. An SRAM cell for providing low leakage current comprising:

a first PMOS transistor having a source connected to a power supply voltage, a gate connected to a first control signal, and a drain connected to a virtual power supply voltage;

a second PMOS transistor having a source connected to the power supply voltage, a gate connected to the virtual power supply voltage and a drain connected to the first control signal;

a first inserted NMOS transistor having a source connected to the first control signal, a gate connected to a second control signal, and a drain connected to the virtual power supply voltage;

a third NMOS transistor having a source and a gate connected to the power supply voltage and a drain connected to the virtual power supply voltage;

a first NMOS transistor having a source connected to the virtual power supply voltage, a gate connected to the virtual power supply voltage, and a drain connected to a ground voltage;

a second NMOS transistor having a source and a gate connected to the virtual power supply voltage, and a drain connected to the ground voltage; and

a fourth NMOS transistor having a source connected to the virtual power supply voltage, a drain and a gate connected to the power supply voltage,

wherein a second inserted NMOS transistor having a source, and a drain connected to the virtual power supply voltage, and a gate connected to the second control signal such that, when the SRAM cell stores bit ‘

1’

, the second inserted NMOS transistor is operatively coupled to provide low leakage currents and when the SRAM cell stores bit ‘

0’

, the first inserted NMOS transistor is operatively coupled to provide low leakage currents.

2. The SRAM cell as claimed in claim 1, wherein said virtual power supply voltage is a voltage level obtained by lowering a power supply voltage by a threshold voltage of a transistor.

3. The SRAM cell as claimed in claim 1, wherein said first control signal and said second control signal are activated, when said SRAM cell is operating in an active mode.

4. The SRAM cell as claimed in claim 1, wherein said second control signal is a power supply voltage.

5. The SRAM cell as claimed in claim 1, wherein said bit line and said complementary bit line are charged at a power supply voltage.

6. The SRAM cell as claimed in claim 1, wherein said bit line and said complementary bit line are precharged to said virtual power supply voltage for reducing a bit-line leakage current.

7. An SRAM array for providing low leakage current comprising:

a plurality of SRAM cells, each of said SRAM cell connected to a word line in a row and in a column to a bit line, a complementary bit line, a power supply voltage, and a ground voltage, wherein each of said SRAM cell comprising;

a first PMOS transistor having a source connected to a power supply voltage, a gate connected to a first control signal, and a drain connected to a virtual power supply voltage;

a second PMOS transistor having a source connected to the power supply voltage, a gate connected to the virtual power supply voltage and a drain connected to the first control signal;

a first inserted NMOS transistor having a source connected to the first control signal, a gate connected to a second control signal, and a drain connected to the virtual power supply voltage;

a third NMOS transistor having a source and a gate connected to the power supply voltage and a drain connected to the virtual power supply voltage;

a first NMOS transistor having a source connected to the virtual power supply voltage, a gate connected to the virtual power supply voltage, and a drain connected to a ground voltage;

a second NMOS transistor having a source and a gate connected to the virtual power supply voltage, and a drain connected to the ground voltage; and

a fourth NMOS transistor having a source connected to the virtual power supply voltage, a drain and a gate connected to the power supply voltage,

wherein a second inserted NMOS transistor having a source, and a drain connected to the virtual power supply voltage, and a gate connected to the second control signal such that, when the SRAM cell stores bit ‘

1’

, the second inserted NMOS transistor is operatively coupled to provide low leakage currents and when the SRAM cell stores bit ‘

0’

, the first inserted NMOS transistor is operatively coupled to provide low leakage currents.

8. The SRAM array as claimed in claim 7, wherein said virtual power supply voltage is a voltage level obtained by lowering said power supply voltage by a threshold voltage of a transistor.

9. The SRAM array as claimed in claim 7, wherein said first control signal and said second control signal are activated, when said SRAM cell is operating in an active mode.

10. The SRAM array as claimed in claim 7, wherein said second control signal is a power supply voltage.

11. The SRAM array as claimed in claim 7, wherein said bit line and said complementary bit line are charged at a power supply voltage.

12. The SRAM array as claimed in claim 7, wherein said bit line and said complementary bit line are precharged to said virtual power supply voltage for reducing a bit-line leakage current.

13. An SRAM memory cell, comprising:

a 6T SRAM memory cell including,

a first PMOS transistor and first NMOS transistor coupled in series between a supply node adapted to receive a supply voltage and a reference node adapted to receive a reference voltage,

a second PMOS transistor and second NMOS transistor coupled in series between the supply and reference nodes;

a first inserted NMOS transistor coupled in series with and between the first PMOS and NMOS transistors;

a second inserted NMOS transistor coupled in series with and between the second PMOS and NMOS transistors, wherein gate nodes of the first and second inserted NMOS transistors are coupled to a control node that is adapted to receive a control signal;

wherein gate nodes of the first and second NMOS transistors are coupled to drains of the second and first inserted NMOS transistors, respectively; and

wherein gate nodes of the first and second PMOS transistors are coupled to sources of the second and first inserted NMOS transistors, respectively.

14. The SRAM memory cell of claim 13 the 6T SRAM memory cell includes first and second NMOS access transistors, each access transistor having a gate adapted to be coupled to a word line and being operable to couple drains of the first and second inserted transistors to a bit line and a complementary bit line, respectively, responsive to a signal on the word line.

15. The SRAM memory cell of claim 14 wherein the bit line and complementary bit lines are each precharged to a virtual power supply voltage that is less than a value of the supply voltage.

16. The SRAM memory cell of claim 14 wherein the bit line and complementary bit lines are each precharged to the supply voltage.

17. The SRAM memory cell of claim 15 wherein the virtual power supply voltage has value equal to the supply voltage minus a threshold voltage of a threshold voltage of the first and second inserted NMOS transistors.

18. The SRAM memory cell of claim 17 is a voltage level obtained by lowering a power supply voltage by a threshold voltage of a transistor.

19. The SRAM memory cell of claim 13 wherein the control signal corresponds to the power supply voltage.

20. The SRAM memory cell of claim 13 wherein the supply voltage corresponds to a positive supply voltage and the reference voltage corresponds to a ground voltage.

21. An electronic device, comprising:

electronic circuitry; and

an array of SRAM memory cells coupled to the electronic circuitry, the memory cells being arranged in rows and columns, each SRAM memory cell in a respective row being coupled to a corresponding word line and each memory cell in a respective column being coupled to corresponding true and complementary bit lines, and each memory cell comprising,

a 6T SRAM memory cell including,

a first PMOS transistor and first NMOS transistor coupled in series between a supply node adapted to receive a supply voltage and a reference node adapted to receive a reference voltage;

a second PMOS transistor and second NMOS transistor coupled in series between the supply and reference nodes;

first and second access transistors coupled between drains of the first and second NMOS transistors and the true and complementary bit lines, respectively, and a gate of each access transistor being coupled to a corresponding word line;

a first inserted NMOS transistor coupled in series with and between the first PMOS and NMOS transistors;

a second inserted NMOS transistor coupled in series with and between the second PMOS and NMOS transistors, wherein gate nodes of the first and second inserted NMOS transistors are coupled to a control node that is adapted to receive a control signal;

wherein gate nodes of the first and second NMOS transistors are coupled to drains of the second and first inserted NMOS transistors, respectively; and

wherein gate nodes of the first and second PMOS transistors are coupled to sources of the second and first inserted NMOS transistors, respectively.

22. The electronic device of claim 21 wherein the electronic circuitry comprises telecommunications circuitry.

23. The electronic device of claim 21 wherein the electronic circuitry comprises computer circuitry.

24. A method of reducing leakage current in an SRAM memory cell, the SRAM memory cell including a first PMOS transistor and first NMOS transistor coupled in series between a supply node adapted to receive a supply voltage and a reference node adapted to receive a reference voltage and including a second PMOS transistor and second NMOS transistor coupled in series between the supply and reference nodes, the method comprising:

when the SRAM memory cell stores a first logic state, providing a virtual power supply voltage at the drain of the second NMOS transistor, the virtual power supply voltage being less than the supply voltage and also being applied to a gate of the first NMOS transistor; and

when the SRAM memory cell stores a second logic state, providing the virtual power supply voltage at the drain of the first NMOS transistor and also applying the virtual power supply voltage to a gate of the second NMOS transistor;

25. The method of claim 24 wherein the first logic state corresponds to a logic 0 and the second logic state corresponds to a logic 1.

26. The method of claim 24 further comprising precharging complementary bit lines coupled to the SRAM memory cell to the virtual power supply voltage.

27. The method of claim 24 further comprising precharging complementary bit lines coupled to the SRAM memory cell to the supply voltage.

28. The method of claim 24 wherein the virtual power supply voltage is equal to the supply voltage minus the threshold voltage of an NMOS transistor.