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8-T SRAM cell circuit, system and method for low leakage current

  • US 20080151605A1
  • Filed: 07/06/2007
  • Published: 06/26/2008
  • Est. Priority Date: 07/06/2006
  • Status: Active Grant
First Claim
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1. An SRAM cell for providing low leakage current comprising:

  • a first PMOS transistor having a source connected to a power supply voltage, a gate connected to a first control signal, and a drain connected to a virtual power supply voltage;

    a second PMOS transistor having a source connected to the power supply voltage, a gate connected to the virtual power supply voltage and a drain connected to the first control signal;

    a first inserted NMOS transistor having a source connected to the first control signal, a gate connected to a second control signal, and a drain connected to the virtual power supply voltage;

    a third NMOS transistor having a source and a gate connected to the power supply voltage and a drain connected to the virtual power supply voltage;

    a first NMOS transistor having a source connected to the virtual power supply voltage, a gate connected to the virtual power supply voltage, and a drain connected to a ground voltage;

    a second NMOS transistor having a source and a gate connected to the virtual power supply voltage, and a drain connected to the ground voltage; and

    a fourth NMOS transistor having a source connected to the virtual power supply voltage, a drain and a gate connected to the power supply voltage,wherein a second inserted NMOS transistor having a source, and a drain connected to the virtual power supply voltage, and a gate connected to the second control signal such that, when the SRAM cell stores bit ‘

    1’

    , the second inserted NMOS transistor is operatively coupled to provide low leakage currents and when the SRAM cell stores bit ‘

    0’

    , the first inserted NMOS transistor is operatively coupled to provide low leakage currents.

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