Flash memory device and system with randomizing for suppressing errors

• US 20080151618A1
• Filed: 06/13/2007
• Published: 06/26/2008
• Est. Priority Date: 12/24/2006
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk IL Ltd. (Western Digital Corporation)
• Inventors: Alrod, Idan, Sharon, Eran
• Granted Patent: US 8,127,200 B2
• Time in Patent Office: Days
• US Class Current: 365/185.02
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

A device for storing data includes a nonvolatile memory and a controller and/or circuitry that randomize original data to be stored in the memory while preserving the size of the original data, that store the original data in the memory, and that, in response to a request for the original data, retrieve, derandomize and export the original data without authenticating the requesting entity. A system for storing data includes a first nonvolatile memory and a processor that similarly stores data in the first nonvolatile memory by executing driver code stored in a second nonvolatile memory. ECC encoding is applied either before or after randomizing; correspondingly, ECC decoding is applied either after or before derandomizing.

Claims

1. A device for storing data, comprising:

(a) a nonvolatile memory; and

(b) a controller, of said nonvolatile memory, operative;

(i) to randomize original data to be stored in said memory while preserving a size of said original data, thereby providing randomized data,

(ii) to store said randomized data in said memory, and

(iii) in response to a request for said original data by an entity external to the device;

(A) to retrieve said randomized data from said memory,

(B) to derandomize said retrieved randomized data, thereby providing retrieved data substantially identical to said original data, and

(C) to export said retrieved data to said entity without authenticating said entity.

2. The device of claim 1, wherein said controller also is operative:

(iv) to apply error correction encoding to said original data prior to said randomizing of said original data; and

(v) to apply error correction decoding to said retrieved data prior to said exporting of said retrieved data.

3. The device of claim 1, wherein said controller also is operative:

(iv) to apply error correction encoding to said randomized data prior to said storing said randomized data in said memory; and

(v) to apply error correction decoding to said retrieved randomized data prior to said derandomizing of said retrieved randomized data.

4. The device of claim 1, wherein said controller is operative to randomize said original data by steps including summing said original data, modulo 2, with a fixed, random bit sequence;

and wherein said controller is operative to derandomize said retrieved randomized data by steps including summing said retrieved randomized data, modulo 2, with said random bit sequence.

5. The device of claim 1, wherein said controller is operative to randomize said original data by steps including summing said original data, modulo 2, with a pseudorandom bit sequence;

and wherein said controller is operative to derandomize said retrieved randomized data by steps including summing said retrieved randomized data, modulo 2, with said pseudorandom bit sequence.

6. The device of claim 5, wherein said pseudorandom bit sequence is fixed.

7. The device of claim 5, wherein said controller is operative to generate said pseudorandom bit sequence.

8. The device of claim 7, wherein said controller is operative to generate said pseudorandom bit sequence using a linear feedback shift register.

9. The device of claim 8, wherein a seed of said linear feedback shift register is fixed.

10. The device of claim 8, wherein said memory is partitioned into units, each said unit having a respective unit number;

and wherein a seed of said linear feedback shift register is a function of said respective unit number of said unit wherein said randomized data are stored.

11. The device of claim 10, wherein said memory is a flash memory and wherein said units are blocks of said flash memory.

12. The device of claim 10, wherein said memory is a flash memory and wherein said units are pages of said flash memory.

13. The device of claim 1, wherein said controller is operative to randomize said original data by steps including scrambling said original data;

and wherein said controller is operative to derandomize said retrieved randomized data by steps including descrambling said retrieved randomized data.

14. The device of claim 13, wherein said scrambling and said descrambling are effected using respective linear feedback shift registers that share a common seed.

15. The device of claim 14, wherein said seed is fixed.

16. The device of claim 14, wherein said memory is partitioned into units, each said unit having a respective unit number;

and wherein said seed is a function of said respective unit number of said unit wherein said randomized data are stored.

17. The device of claim 16, wherein said memory is a flash memory and wherein said units are blocks of said flash memory.

18. The device of claim 16, wherein said memory is a flash memory and wherein said units are pages of said flash memory.

19. A device for storing data, comprising:

(a) a memory that includes;

(i) an array of nonvolatile memory cells, and

(ii) circuitry operative;

(A) to randomize original data that are to be stored in said memory cells while preserving a size of said original data, thereby providing randomized data,

(B) to store said randomized data in at least a portion of said memory cells,

(C) to retrieve said randomized data from said at least portion of said memory cells, and

(D) to derandomize said retrieved randomized data, thereby providing retrieved data substantially identical to said original data; and

(b) a controller operative;

(i) in response to a request for said original data from an entity external to the device, to export said retrieved data to said entity without authenticating said entity.

20. The device of claim 19, wherein said controller also is operative:

(ii) to apply error correction encoding to said original data prior to said randomizing of said original data; and

(iii) to apply error correction decoding to said retrieved data prior to said exporting of said retrieved data.

21. The device of claim 19, wherein said circuitry is operative to randomize said original data by steps including summing said original data, modulo 2, with a fixed, random bit sequence;

and wherein said circuitry is operative to derandomize said retrieved randomized data by steps including summing said retrieved randomized data, modulo 2, with said random bit sequence.

22. The device of claim 19, wherein said circuitry is operative to randomize said original data by steps including summing said original data, modulo 2, with a pseudorandom bit sequence;

and wherein said circuitry is operative to derandomize said retrieved randomized data by steps including summing said retrieved randomized data, modulo 2, with said pseudorandom bit sequence.

23. The device of claim 22, wherein said pseudorandom bit sequence is fixed.

24. The device of claim 22, wherein said circuitry is operative to generate said pseudorandom bit sequence.

25. The device of claim 24, wherein said circuitry includes a linear feedback shift register for generating said pseudorandom bit sequence.

26. The device of claim 25, wherein a seed of said linear feedback shift register is fixed.

27. The device of claim 25, wherein said memory array is partitioned into units, each said unit having a respective unit number;

wherein said at least portion of said memory cells is one of said units and wherein a seed of said linear feedback shift register is a function of said respective unit number of said one unit.

28. The device of claim 27, wherein said memory cells are flash memory cells and wherein said units are blocks of said flash memory cells.

29. The device of claim 27, wherein said memory cells are flash memory cells and wherein said units are pages of said flash memory cells.

30. The device of claim 19, wherein said circuitry includes:

(A) a scrambler block for randomizing said original data; and

(B) a descrambler block for derandomizing said retrieved randomized data.

31. The device of claim 30, wherein said scrambler block and said descrambler block are implemented as respective linear feedback shift registers that share a common seed.

32. The device of claim 31, wherein said seed is fixed.

33. The device of claim 31, wherein said memory array is partitioned into units, each said unit having a respective unit number;

wherein said at least portion of said memory cells is one of said units; and

wherein said seed is a function of said respective unit number of said one unit.

34. The device of claim 33, wherein said memory cells are flash memory cells and wherein said units are blocks of said flash memory cells.

35. The device of claim 33, wherein said memory cells are flash memory cells and wherein said units are pages of said flash memory cells.

39. The system of claim 34, wherein said code for randomizing said original data includes code for summing said original data, modulo 2, with a fixed, random bit sequence, and wherein said code for derandomizing said retrieved randomized data includes code for summing said retrieved randomized data, modulo 2, with said random bit sequence.

36. A system for storing data, comprising:

(a) a first nonvolatile memory;

(b) a second nonvolatile memory wherein is stored a driver for said first nonvolatile memory, said driver including;

(i) code for randomizing original data to be stored in said first nonvolatile memory while preserving a size of said original data, thereby providing randomized data,

(ii) code for storing said randomized data in said first nonvolatile memory, and

(iii) code for responding to a request for said original data by;

(A) retrieving said randomized data from said first nonvolatile memory,

(B) derandomizing said retrieved randomized data, thereby providing retrieved data substantially identical to said original data, and

(C) exporting said retrieved data without authenticating said request; and

(c) a processor for executing said code of said driver.

37. The system of claim 36, wherein said driver further includes:

(iv) code for applying error correction encoding to said original data prior to said randomizing of said original data; and

(v) code for applying error correction decoding to said retrieved data prior to said exporting of said retrieved data.

38. The system of claim 36, wherein said driver further includes:

(iv) code for applying error correction encoding to said randomized data prior to said storing said randomized data in said memory; and

(v) code for applying error correction decoding to said retrieved randomized data prior to said derandomizing of said retrieved randomized data.

40. The system of claim 36, wherein said code for randomizing said original data includes code for summing said original data, modulo 2, with a pseudorandom bit sequence, and wherein said code for derandomizing said retrieved randomized data includes code for summing said retrieved randomized data, modulo 2, with said pseudorandom bit sequence.

41. The system of claim 40, wherein said pseudorandom bit sequence is fixed.

42. The system of claim 40, wherein said driver further includes:

(iv) code for generating said pseudorandom bit sequence.

43. The system of claim 42, wherein said code for generating said pseudorandom bit sequence includes code of a linear feedback shift register.

44. The system of claim 43, wherein a seed of said linear feedback shift register is fixed.

45. The system of claim 43, wherein said first nonvolatile memory is partitioned into units, each said unit having a respective unit number;

and wherein a seed of said linear feedback shift register is a function of said respective unit number of said unit wherein said randomized data are stored.

46. The system of claim 45, wherein said first nonvolatile memory is a flash memory and wherein said units are blocks of said flash memory.

47. The system of claim 45, wherein said first nonvolatile memory is a flash memory and wherein said units are pages of said flash memory.

48. The system of claim 36, wherein said code for randomizing said original data includes code for scrambling said original data;

and wherein said code for derandomizing said retrieved randomized data includes code for descrambling said retrieved randomized data.

49. The system of claim 48, wherein said code for scrambling said original data includes respective linear feedback shift code;

wherein said code for descrambling said retrieved randomized data includes respective linear feedback shift code; and

wherein both said linear feedback shift codes share a common seed.

50. The system of claim 49, wherein said seed is fixed.

51. The system of claim 49, wherein said first nonvolatile memory is partitioned into units, each said unit having a respective unit number;

and wherein said seed is a function of said respective unit number of said unit wherein said randomized data are stored.

52. The system of claim 51, wherein said first nonvolatile memory is a flash memory and wherein said units are blocks of said flash memory.

53. The system of claim 51, wherein said first nonvolatile memory is a flash memory and wherein said units are pages of said flash memory.

54. A computer-readable storage medium having computer-readable code embedded thereon, the computer-readable code being driver code for a memory device, the computer-readable code comprising:

(a) program code for randomizing original data to be stored in a memory of the memory device while preserving a size of the original data, thereby providing randomized data;

(b) program code for storing said randomized data in said memory; and

(c) program code for responding to a request for said original data by;

(i) retrieving said randomized data from said memory,

(ii) derandomizing said retrieved randomized data, thereby providing retrieved data substantially identical to said original data, and

(iii) exporting said retrieved data without authenticating said request.

55. A device for storing data, comprising:

(a) a nonvolatile memory having a sufficient number of memory cells to store original data by programming said memory cells to a set of corresponding states of said memory cells; and

(b) a controller, of said nonvolatile memory, operative;

(i) to map said original data into a set of states of all said memory cells that is randomized relative to said set of corresponding states,

(ii) to instruct said memory to program said memory cells to said randomized set of states, and

(iii) in response to a request for said original data by an entity external to the device;

(A) to read said memory cells, thereby providing retrieved randomized data,

(B) to derandomize said retrieved randomized data, thereby providing retrieved data substantially identical to said original data, and

(C) to export said retrieved data to said entity without authenticating said entity.

56. The device of claim 55, wherein said states of said memory cells occur in said randomized set of states in substantially equal numbers.

57. A device for storing data, comprising:

(a) a memory that includes;

(i) a sufficient number of memory cells to store original data by programming said memory cells to a set of corresponding states of said memory cells, and

(ii) circuitry operative;

(A) to map said original data into a set of states of all said memory cells that is randomized relative to said set of corresponding states,

(B) to program said memory cells to said randomized set of states,

(C) to read said memory cells, thereby providing retrieved randomized data, and

(D) to derandomize said retrieved randomized data, thereby providing retrieved data substantially identical to said original data; and

(b) a controller operative, in response to a request for said original data from an entity external to the device, to export said retrieved data to said entity without authenticating said entity.

58. The device of claim 57, wherein said states of said memory cells occur in said randomized set of states in substantially equal numbers.

59. A system for storing data, comprising:

(a) a first nonvolatile memory having a sufficient number of memory cells to store original data by programming said memory cells to a set of corresponding states of said memory cells;

(b) a second nonvolatile memory wherein is stored a driver for said first nonvolatile memory, said driver including;

(i) code for mapping said original data into a set of states of all said memory cells that is randomized relative to said set of corresponding states,

(ii) code for instructing said first nonvolatile memory to program said memory cells to said randomized set of states, and

(iii) code for responding to a request for said original data by;

(A) instructing said first nonvolatile memory device to read said memory cells, thereby providing retrieved randomized data,

(B) derandomizing said retrieved randomized data, thereby providing retrieved data substantially identical to said original data, and

(C) exporting said retrieved data without authenticating said request; and

(c) a processor for executing said code of said driver.

60. The system of claim 59, wherein said states of said memory cells occur in said randomized set of states in substantially equal numbers.

61. A computer-readable storage medium having computer-readable code embedded thereon, the computer-readable code being driver code for a memory device that includes a sufficient number of memory cells to store original data by programming the memory cells to a set of corresponding states of the memory cells, the computer-readable code comprising:

(a) program code for mapping the original data into a set of states of all the memory cells that is randomized relative to the set of corresponding states;

(b) program code for instructing the memory device to program the memory cells to said randomized set of states; and

(c) program code for responding to a request for the original data by;

(i) instructing the memory device to read the memory cells, thereby providing retrieved randomized data,

(ii) derandomizing said retrieved randomized data, thereby providing retrieved data substantially identical to the original data, and

(iii) exporting said retrieved data without authenticating said request.

62. The computer-readable storage medium of claim 61, wherein said states of said memory cells occur in said randomized set of states in substantially equal numbers.