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Command-based control of NAND flash memory

  • US 20080151622A1
  • Filed: 12/21/2006
  • Published: 06/26/2008
  • Est. Priority Date: 12/21/2006
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • an array of non-volatile memory cells; and

    an interface coupled to the array and containing a set of input/output signal pins and a clock signal pin;

    wherein the array is to be controlled through the interface by placing command signals, address signals, and data signals on the same set of input/output signal pins, and using the clock signal to latch the command signals, address signals, and data signals.

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