Command-based control of NAND flash memory

• US 20080151622A1
• Filed: 12/21/2006
• Published: 06/26/2008
• Est. Priority Date: 12/21/2006
• Status: Active Grant

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Eilert, Sean S., Qawami, Shekoufeh, Rozman, Rodney R.
• Granted Patent: US 7,802,061 B2
• Time in Patent Office: Days
• US Class Current: 365/185.05
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

Some embodiments of the invention use a command-based interface to control reads and writes with non-volatile memory devices. This may reduce the number of pins that are needed on each integrated circuit, and therefore reduce the cost and size of those integrated circuits. In some embodiments, an on-die cache buffer may be used to buffer data transfers between a high-speed memory bus and the slower speed non-volatile array.

Claims

1. An apparatus, comprising:

an array of non-volatile memory cells; and

an interface coupled to the array and containing a set of input/output signal pins and a clock signal pin;

wherein the array is to be controlled through the interface by placing command signals, address signals, and data signals on the same set of input/output signal pins, and using the clock signal to latch the command signals, address signals, and data signals.

2. The apparatus of claim 1, wherein the array is a NAND flash array.

3. The apparatus of claim 1, wherein:

the command signals are to be placed on the input/output pins during a first set of clock cycles;

the address signals are to be placed on the input/output pins during a second set of clock cycles subsequent to the first set; and

the data signals are to be placed on the input/output pins during a third set of clock cycles subsequent to the second set.

4. The apparatus of claim 3, where the first set of clock cycles are to consist of a single clock cycle.

5. The apparatus of claim 1, wherein the command signals are to include signals indicating whether the command is a read command or a write command and to indicate a length of the second and third sets.

6. The apparatus of claim 1, wherein the interface further includes another pin to carry a signal to indicate a start of the first set.

7. The apparatus of claim 1, wherein the interface does not include any pin devoted solely to indicating either of an address latch or a read/write select.

8. The apparatus of claim 1, further comprising a host device coupled to the interface to communicate the command signals to the interface, the host device not contained in a same integrated circuit as the interface.

9. A method, comprising:

receiving a command for operation of a non-volatile memory device on a set of input/output lines, the command indicating a read operation or a write operation;

receiving an address on the set of input/output lines subsequent to receiving the command, the address indicating a starting location of a data transfer operation; and

receiving data on the set of input/output lines subsequent to receiving the address, the data to be transferred to or from a block of addresses in the non-volatile memory device starting with the received address;

wherein a single clock signal is used to latch the address and data.

10. The method of claim 9, wherein another signal is used to latch the command.

11. The method of claim 9, wherein said receiving a command comprises receiving a command for operation of a NAND flash memory device.

12. The method of claim 9, wherein:

said receiving the command comprises interpreting signals on the input/output lines as a command for a first number of clock cycles;

said receiving the address comprises interpreting signals on the input/output lines as an address for a second number of clock cycles; and

said receiving the data comprises interpreting signals on the input/output lines as data for a third number of clock cycles.

13. The method of claim 12, wherein the third number of clock cycles is indicated in the command.

14. The method of claim 9, further comprising automatically returning to a receive mode of operation to said receiving the data.

15. An article comprising

a tangible machine-readable medium that contains instructions, which when executed by one or more processors result in performing operations comprising:

sending a first set of signals on a set of input/output lines from a host device to a non-volatile memory device, the first set of signals to indicate a command to the non-volatile memory device;

sending a second set of signals on the set of input/output lines from the host device to the non-volatile memory device, the second set of signals to indicate a starting address for a data transfer with the non-volatile memory device;

transferring a third set of signals on the set of input/output lines between the host device and the non-volatile memory device, the third set of signals to indicate the data for the data transfer; and

providing a single clock signal to synchronize the second and third sets of signals.

16. The article of claim 15, further comprising the operation of providing another signal to synchronize the first set of signals.

17. The article of claim 15, further comprising the operation of including information in the first set of signals to indicate a length of the third set of signals.

18. The article of claim 15, wherein a length of the first set of signals is predetermined.

19. The article of claim 15, wherein a length of the second set of signal is predetermined.

20. An apparatus, comprising:

a non-volatile memory array comprising;

a storage array of non-volatile memory cells;

a cache buffer coupled to the array to buffer data transfers between the array and a memory controller; and

control logic coupled to the array and to the cache buffer, to control the data transfers into and out of the storage array.

21. The apparatus of claim 20, wherein the array comprises NAND flash memory cells.

22. The apparatus of claim 20, wherein the cache buffer is able to hold at least a page of data.

23. The apparatus of claim 20, wherein the cache buffer comprises a first-in first-out buffer.

24. A method, comprising:

transferring data synchronously between a memory controller and a cache buffer in a NAND flash memory device; and

transferring the data between the cache buffer and a storage array in the NAND flash memory device.

25. The method of claim 24, wherein:

said transferring the data between the memory controller and the cache buffer comprises transferring the data from the memory controller to the cache buffer; and

said transferring the data between the cache buffer and the storage array comprises transferring the data from the cache buffer to the storage array.

26. The method of claim 24, wherein:

said transferring the data between the cache buffer and the storage array comprises transferring the data from the storage array to the cache buffer; and

said transferring the data between the memory controller and the cache buffer comprises transferring the data from the cache buffer to the memory controller.