JITTER AMPLIFIER CIRCUIT, SIGNAL GENERATION CIRCUIT, SEMICONDUCTOR CHIP, AND TEST APPARATUS

• US 20080151981A1
• Filed: 12/25/2006
• Published: 06/26/2008
• Est. Priority Date: 12/25/2006
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Ichiyama, Kiyotaka, Ishida, Masahiro
• Granted Patent: US 8,045,605 B2
• Time in Patent Office: Days
• US Class Current: 375/226
• CPC Class Codes: G01R 31/31709 Jitter measurements; Jitter generators measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901

Abstract

There is provided a jitter amplifier circuit for amplifying jitter included in an input signal. The jitter amplifier circuit includes a distorting circuit that receives the input signal, and distorts a waveform of the input signal so as to generate a harmonic component of the input signal, and a filter that passes, out of the distorted signal output from the distorting circuit, a harmonic component of a certain order which is determined in accordance with an amplification ratio of amplifying the jitter.

Claims

1. A jitter amplifier circuit for amplifying jitter included in an input signal, comprising:

a distorting circuit that receives the input signal, and distorts a waveform of the input signal so as to generate at least a harmonic component of the input signal; and

a filter that passes, out of the distorted signal output from the distorting circuit, a harmonic component of a certain order which is determined in accordance with an amplification ratio of amplifying the jitter.

2. The jitter amplifier circuit as set forth in claim 1, wherein,

the distorting circuit includes therein an n-th power circuit (n is an integer of two or more) that raises the input signal to the n-th power which is determined in accordance with the amplification ratio of amplifying the jitter, and

the filter passes an n-th harmonic component of the distorted signal.

3. The jitter amplifier circuit as set forth in claim 1, wherein,

the input signal is a sine curve, and

the distorting circuit outputs a rectangular wave in synchronization with a timing at which the input signal reaches a predetermined level.

4. A signal generation circuit for generating an output signal including jitter injected thereto, comprising:

a reference signal generating section that generates a reference signal;

a jitter injecting section that injects jitter into the reference signal output from the reference signal generating section; and

a jitter amplifier circuit that receives the reference signal including the jitter injected thereto by the jitter injecting section, and amplifies the jitter included in the reference signal, wherein

the jitter amplifier circuit includes;

a distorting circuit that receives the reference signal including the jitter injected thereto by the jitter injecting section, and distorts a waveform of the received reference signal so as to generate at least a harmonic component of the reference signal; and

a filter that passes, out of the distorted signal output from the distorting circuit, a harmonic component of a certain order which is determined in accordance with an amplitude of the jitter to be injected into the output signal.

5. The signal generation circuit as set forth in claim 4, wherein,

the filter passes an n-th harmonic component (n is an integer of two or more) of the distorted signal, and

the reference signal generating section generates the reference signal having a frequency equal to one n-th of a frequency to be possessed by the output signal.

6. A semiconductor chip for amplifying jitter included in an input signal, comprising:

a distorting circuit that receives the input signal, and distorts a waveform of the input signal so as to generate at least a harmonic component of the input signal; and

a filter that passes, out of the distorted signal output from the distorting circuit, a harmonic component of a certain order which is determined in accordance with an amplification ratio of amplifying the jitter.

7. A test apparatus for testing a device under test comprising,

a pattern generating section that generates a predetermined logic pattern;

a signal generation circuit that generates a clock signal including jitter injected thereto;

a waveform shaping section that generates a test signal by sampling the logic pattern in accordance with the clock signal, and inputs the generated test signal into the device under test; and

a judging section that judges acceptability of the device under test based on a to-be-measured signal output from the device under test in response to the test signal, wherein

the signal generation circuit includes;

a reference signal generating section that generates a reference signal;

a jitter injecting section that injects jitter to the reference signal output from the reference signal generating section; and

a jitter amplifier circuit that receives the reference signal including the jitter injected thereto by the jitter injecting section, and

the jitter amplifier circuit includes;

a distorting circuit that receives the reference signal including the jitter injected thereto by the jitter injecting section, and distorts a waveform of the received reference signal so as to generate at least a harmonic component of the reference signal; and

a filter that passes, out of the distorted signal output from the distorting circuit, a harmonic component of a certain order which is determined in accordance with an amplitude of the jitter to be injected into the clock signal, so as to generate the clock signal.