Multi-pair gigabit ethernet transceiver
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Accused Products
Abstract
Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter'"'"'s partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
79 Citations
167 Claims
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1-16. -16. (canceled)
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17. An integrated circuit communication device comprising:
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an intersymbol interference (ISI) compensation filter having a substantially inverse impulse response to the impulse response of a pulse shaping filter of a remote transmitter; and an adaptive gain stage.
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18-159. -159. (canceled)
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160. An integrated circuit communication device comprising:
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a multi-state decoder operable to receive a multi-state representation signal and to generate tentative decisions and a final decision based on the received multi-state representation signal; a single-state decision feedback equalizer operable to receive at least one tentative decision from the multi-state decoder, the at least one tentative decision corresponding to a single state of the multi-state decoder, and operable to generate a single-state intersymbol interference (ISI) compensation signal based on the at least one tentative decision; a combiner operable to combine the single-state ISI compensation signal with an input signal to produce a single-state representation signal; and a state multiplication circuit operable to expand the single-state representation signal received from the single-state decision feedback equalizer into a multi-state representation signal suitable for decoding by the multi-state decoder. - View Dependent Claims (161, 162, 163, 164, 165, 166, 167)
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Specification