Multi-path switching networks

• US 20080155127A1
• Filed: 10/05/2007
• Published: 06/26/2008
• Est. Priority Date: 10/05/2006
• Status: Abandoned Application

• Current Assignee: John M. Holt
• Original Assignee: John M. Holt
• Inventors: Holt, John M.
• Application Number:
  US11/973,317
• Publication Number:
  US 20080155127A1
• Time in Patent Office: Days
• US Class Current: 709/252
• CPC Class Codes: H04L 49/1515 Non-blocking multistage, e.g. Clos

Abstract

A switching network for multiple computer systems is disclosed which utilises pairs of multi-port switches (S1-S4) and (preferably) less complex switches (S5-S7). The multi-port switches are arranged in pairs with a computer of the multiple computer system being able to be connected to each port of each multi-port switch except for one port. That one port of each multi-port switch is connected to a single one of the less complex switches. All the less complex switches are arranged in a twin branch multi-level tree structure. The arrangement overcomes bottlenecks arising from the serial interconnection of multi-port switches.

Claims

1. A multiple computer system comprising:

a plurality of computers interconnected by a communications network, said plurality of computers adapted for substantially simultaneous executing of different portions of least one application program each written to operate only on a single conventional computer, each of said plurality of computers further including a local processor executing instructions of at least a portion of at least one application program and a local memory coupled to said local processor; and

a switching network comprising;

a first plurality of multi-port switches and a second plurality of switches;

said multi-port switches being arranged in pairs with a computer of said plurality of computers of said multiple computer system being connectable to each port of each multi-port switch except one port;

said one port of each pair of multi-port switches being connected to a single one of said second plurality of switches; and

all said second plurality of switches being arranged in a twin branch multi-level tree structure.

2. The multiple computer system as in claim 1, wherein each of said second plurality of switches is a less complex switch than said multi-port switches.

3. The multiple computer system as in claim 2, wherein said pairs of multi-port switches are symmetrically arranged with respect to the less complex switch of the lowest level of said tree structure.

4. The multiple computer system as in claim 3, wherein said less complex switch of the lowest level of said tree structure comprises a two port switch and all the other of said less complex switches comprise three port switches.

5. The multiple computer system as in claim 1, wherein the multiple computer system is configured to operate as one of:

(i) a replicated shared memory computer system, (ii) a hybrid or partial shared memory computer system, and (iii) a distributed shared memory multiple computer system.

6. A method of connecting and operating a multiple computer system that includes a plurality of computers, said method comprising:

interconnecting said plurality of computers using a communications network, said plurality of computers each including a local processor and a local memory coupled to the processor;

providing or enabling for operation a first plurality of multi-port switches and a second plurality of switches, each multi-port switch including a plurality of ports; and

arranging said first plurality of multi-port switches and said second plurality of switches in pairs with a computer of said plurality of computers being at least intermittently connected to each port of each multi-port switch except one differently connected port;

said one differently connected port of each pair of multi-port switches being connected to a single one of said second plurality of switches; and

all said second plurality of switches being arranged in a twin branch multi-level tree structure.

7. A single computer comprising:

a processor and a memory coupled to said processor; and

a communications port for coupling said single computer to an external communications network to which is at least intermittently coupled at least one other external computer;

said single computer being adapted for at least intermittent connection to an external switching network that includes a first plurality of multi-port switches and a second plurality of switches;

said single computer being connectable to a port of each multi-port switch except one port, and said one port being connected to a single one of said second plurality of switches.

8. The single computer as in claim 7, wherein each of said second plurality of switches is a less complex switch than said multi-port switches.