Host System With Direct Data File Interface Configurability

• US 20080155176A1
• Filed: 12/26/2006
• Published: 06/26/2008
• Est. Priority Date: 12/26/2006
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Sinclair, Alan W., Wright, Barry
• Granted Patent: US 7,917,686 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

Data files are assigned addresses within one or more logical blocks of a continuous logical address space interface (LBA interface) of a usual type of flash memory system with physical memory cell blocks. This assignment may be done by the host device which typically, but not necessarily, generates the data files. The number of logical blocks containing data of any one file is controlled in a manner that reduces the amount of fragmentation of file data within the physical memory blocks, thereby to maintain good memory performance. The host may configure the logical blocks of the address space in response to learning the physical characteristics of a memory to which it is connected.

Claims

1. A computer system, comprising:

an internal memory capable of storing data of at least one file object,

an interface adapted for connection to a non-volatile memory system thereto that includes a memory cell array organized into blocks of memory cells that are erasable together, and

a processor programmed to perform at least the following functions;

read information from a memory system externally connected to the interface about the memory cell block structure of the connected memory,

define a continuous logical address space at the interface that includes blocks of addresses having characteristics corresponding to the external memory cell block organization read from memory system connected therewith,

assign unique addresses within the blocks of the defined logical address space to data file objects stored in the internal memory, and

transfer the data file objects through the interface with the assigned logical addresses.

2. The computer system of claim 1, wherein the processor is further programmed to assign addresses to individual data objects in no more than a preset number of logical blocks that contain addresses of another data file object.

3. The computer system of claim 2, wherein the preset number is two.

4. The computer system of claim 1, wherein the processor is further programmed to:

maintain a first record for the individual logical blocks

maintaining a second record for the individual stored data file objects of one of a plurality of file states that are based upon how data of the file are distributed among one or more of a plurality of types of logical blocks, and

writing additional data of a given one of the data file objects to a type of logical block that is selected based upon the state in the second record of the given file.

5. The computer system of claim 1, wherein the processor is further programmed to:

read, from an external memory attached to the interface, information of the data storage capacity of the individual memory cell blocks and to define the continuous logical address space with individual blocks of addresses representing the same amount of data as are stored in the individual memory cell, and

read, from an external memory attached to the interface, the lowest logical addresses of the logical blocks that are mapped from the interface to the lowest physical address of corresponding memory cell blocks beginning data storage addresses and to define the logical blocks with beginning logical addresses aligned with the beginning memory cell block data storage addresses.

6. The computer system of claim 1, wherein the interface is further adapted for removable connection of the non-volatile memory system.