SYSTEMS AND METHODS FOR REDUCING WIRING VIAS DURING SYNTHESIS OF ELECTRONIC DESIGNS

• US 20080155486A1
• Filed: 12/20/2006
• Published: 06/26/2008
• Est. Priority Date: 12/20/2006
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Trevillyan, Louise H.
• Application Number:
  US11/613,754
• Publication Number:
  US 20080155486A1
• Time in Patent Office: Days
• US Class Current: 716/9
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

Systems and methods for reducing wire vias during synthesis of electronic designs. Exemplary embodiments include an electronic design via reduction method, including marking a plurality of nets, each net having at least two pin connections as unprocessed, determining whether there are further unprocessed nets, selecting one of the plurality of nets and marking the net as processed, sorting pairs of pins on the net by a displacement, selecting an unprocessed pin pair having the smallest displacement relative to other of the plurality of unprocessed pin pairs, selectively removing a via between the pins, determining whether there are any further unprocessed pin pairs and determining whether there are any further unprocessed nets.

Claims

1. An electronic design via reduction method, comprising:

marking a plurality of nets, each net having at least two pin connection as unprocessed;

determining whether there are further unprocessed nets;

selecting one of the plurality of nets and marking the net as processed;

sorting pairs of pins on the net by a displacement;

selecting an unprocessed pin pair having the smallest displacement relative to other of the plurality of unprocessed pin pairs;

selectively removing a via between the pins;

determining whether there are any further unprocessed pin pairs; and

determining whether there are any further unprocessed nets.

2. The method as claimed in claim 1 further comprising determining whether each of the pins in the pin pair is at least one of fixed and in a same circuit row

3. The method as claimed in claim 2 wherein selecting an unprocessed pair with the smallest displacement occurs if the pin pair is not at least one of fixed and in the same circuit row.

4. The method as claimed in claim 3 further comprising computing a displacement N between the pins of the pin pair.

5. The method as claimed in claim 4 further comprising determining if N is below a predetermined displacement threshold.

6. The method as claimed in claim 5 further comprising:

selecting boxes attached to the pins; and

determining a leftmost box and a rightmost box.

7. The method as claimed in claim 6 further comprising in response to the leftmost box and rightmost box being unfixed, computing a move interval.

8. The method as claimed in claim 7 further comprising selecting a displacement relative to the move interval such that a displacement of the leftmost box and the rightmost box fall within a set of constraints.

9. The method as claimed in claim 8 wherein the set of constraints are selected from the group consisting of:

a move must not make a critical slack worse;

a move must not cause an electrical violation;

a move must not cause a placement overlap;

a move must not cause a box to be placed illegally;

a move must not increase the number of vias in the pattern; and

a move must not cause large increases in the wire length of the design.

10. The method as claimed in claim 9 further comprising in response to at least the placement of the leftmost and rightmost boxes being displaced within constraints, computing new bend information for all nets connected to the leftmost and rightmost boxes.

11. The method as claimed in claim 10 further comprising marking both of the pins in the pin pair as fixed if the bends have been reduced.

12. A computer readable medium having computer executable instructions for performing an electronic design via reduction method, comprising:

marking a plurality of nets, each net having at least two pin connections as unprocessed;

determining whether there are further unprocessed nets;

selecting one of the plurality of nets and marking the net as processed;

sorting pairs of pins on the net by a displacement;

determining that there are no further unprocessed pin pairs;

selecting an unprocessed pin pair having the smallest displacement relative to other of the plurality of unprocessed pin pairs.

defining a identification procedure to determine whether the pin pairs are in at least one of fixed and in the same circuit row;

recursively using said identification procedure until no further pin pairs are identifies as at least one of fixed and in the same circuit row;

computing a displacement N between the pins of the pin pair;

defining a displacement procedure to determine if N has exceeded a predetermined threshold;

recursively using said displacement procedure while N has not exceeded the predetermined threshold;

defining a constraints procedure that includes;

defining a move interval;

recursively applying the constrains procedure to determine a location for the leftmost box and shifting the leftmost box along the move interval until it aligns with the rightmost box;

recursively applying the constraints procedure to determine a location for the rightmost box and shifting the rightmost box along the move interval until it aligns with the leftmost box;

determining whether the leftmost and rightmost boxes are positioned in locations within bounds of pre-determined constraints; and

determining if there are any further unprocessed nets.

13. A method for reducing vias during synthesis of electronic designs, the method comprising:

selecting a plurality of nets, each net having at least two pin connections;

counting a total number of vias for boxes to which all the pins on the nets are attached;

determining a slack and violation ration on each of the plurality of nets;

ranking pairs of pins on each net by an offset of a horizontal position of the pins;

recursively selecting pins in an order of increasing offset, wherein the offset determines a window in which boxes may be positioned;

selectively sliding rightmost and leftmost boxes to determine an alignment of the boxes within pre-determined constraints;

selecting the window such that it is within a predetermined displacement; and

determining that the pins are in alignment within the predetermined constraints.

14. The method as claimed in claim 13 wherein the predetermined constraints are selected from the group consisting of:

a move must not make a critical slack worse;

a move must not cause an electrical violation;

a move must not cause a placement overlap;

a move must not cause a box to be placed illegally;

a move must not increase the number of vias in the pattern; and

a move must not cause large increases in the wire length of the design.

15. The method as claimed in claim 14 further comprising determining that the search window has been exhausted.

16. The method as claimed in claim 15 further comprising:

determining if either of the pins of the pin pair is fixed, and determining whether or not bends on the net have been reduced in response to neither of the pins being fixed.

17. The method as claimed in claim 16 further comprising determining that there are no remaining unprocessed pin pairs.

18. The method as claimed in claim 17 wherein the unprocessed pin pair with a displacement smallest relative to remaining pin pair is selected.

19. The method as claimed in claim 18 further comprising fixing the rightmost and leftmost boxes.

20. The method as claimed in claim 19 further comprising determining that there are any remaining unprocessed nets.