Semiconductor memory device and method of manufacturing the same

• US 20080157168A1
• Filed: 12/05/2007
• Published: 07/03/2008
• Est. Priority Date: 12/27/2006
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Mizukoshi, Toshikazu
• Granted Patent: US 8,154,070 B2
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile memory includes a semiconductor substrate having a body member and a step member formed on the body member, a highly doped first well layer formed on the step member, a control electrode formed on the step member, a first and a second diffusion layers in the substrate, lightly doped second well layers formed on the main surface of the substrate between the first or the second diffusion layer and the first well layer, and a first and a second charge-storage multi-layers sandwiching the step member and the control electrode, each of the first and the second charge-storage multi-layers including a bottom oxide layer, a charge-storage film, a top oxide layer and a floating electrode which are formed in that order.

Claims

1. A nonvolatile semiconductor memory, comprising:

a semiconductor substrate having a step member formed on its main surface, the step member having an upper surface;

a first well layer having a first conductive type formed on the upper surface of the step member;

a control electrode formed on the step member via a gate oxide layer, which is formed on the first well layer;

a first and a second diffusion layers each having a second conductive type, which is different from the first conductive type, the first and the second diffusion layers being formed on the main surface of the semiconductor substrate in areas, which are located at both sides of an area where the step member is formed;

second well layers each having the first conductivity type, one of the second well layers being formed on the main surface of the semiconductor substrate between the first diffusion layer and the first well layer, and the other second well layer being formed on the main surface of the semiconductor substrate between the second diffusion layer and the first well layer, wherein the concentration of the first conductivity type in either the second well layers is lighter than that in the first well layer; and

a first and a second charge-storage multi-layers sandwiching the step member and the control electrode, each of the first and the second charge-storage multi-layers including a bottom oxide layer, a charge-storage film formed on the bottom oxide layer, a top oxide layer formed on the charge-storage film and a floating electrode formed on the top oxide layer.

2. A nonvolatile semiconductor memory as claimed in claim 1, wherein a height of the step member is larger than the sum of the thickness of the bottom oxide layer, the thickness of the charge-storage film and the thickness of the top oxide layer in each of the first and the second charge-storage multi-layers.

3. A nonvolatile semiconductor memory as claimed in claim 1, wherein a height of the step member is set in the range between 30 nm and 50 nm.

4. A nonvolatile semiconductor memory as claimed in claim 1, wherein a top surface of the floating gate in each of the first and the second charge-storage multi-layers is located lower than a top surface of the control electrode.

5. A nonvolatile semiconductor memory as claimed in claim 1, wherein the bottom oxide layer, the charge-storage film and the top oxide layer in each of the first and the second charge-storage multi-layers are L-letter-shaped.

6. A nonvolatile semiconductor memory as claimed in claim 5, wherein the floating electrode in each of the first and the second charge-storage multi-layers are I-letter-shaped.

7. A nonvolatile semiconductor memory as claimed in claim 1, wherein the step member is the first step member, further comprising at least two more step members, wherein each step member is extended in the same direction, is disposed in parallel to each other, and is spaced at regular intervals.

8. A method of manufacturing a nonvolatile semiconductor memory, comprising:

preparing a semiconductor substrate having on its main surface a first well in which impurities of a first conductive type are implanted, and defining a convex region and flat regions sandwiching the step region;

forming a first silicon oxide layer, a first charge-storage film, a first silicon nitride layer on the main surface of the semiconductor substrate in that order;

patterning the first silicon nitride layer for forming a nitride layer mask, which covers the convex region;

patterning the first charge-storage film for forming a control electrode, by using the nitride layer mask;

forming a gate oxide layer under the control electrode by removing the first oxide layer in the flat region by using the nitride layer mask and the control gate as a mask, and forming a step member on the main surface of the semiconductor substrate by removing the first well layer in the flat region and by further removing a part of the semiconductor substrate in the flat region from its main surface, whereby the semiconductor substrate includes the step member and a body member located under the step member;

forming a second silicon oxide layer on the semiconductor substrate in the flat region and on the side surfaces of the step member, of the gate oxide layer, of the first well layer and of the control electrode;

forming second well layers by implanting impurities of the first conductivity, each second well layer being extended from the surface of the semiconductor substrate in the flat region to the side surface of the step member;

forming a second silicon nitride later, a third silicon oxide later and a second conductive layer on the second silicon oxide layer in that order;

forming floating gates from the second conductive layer by etching on the side surfaces of the step member, of the gate oxide layer, of the first well layer and of a part of the control electrode;

forming a third silicon nitride layer, which covers the floating gates, on the silicon oxide layer;

forming charge-storage multi-layers from the second silicon oxide layer, the second silicon nitride layer, the third silicon oxide layer and the third silicon nitride layer by anisotropic-etching them partially in the flat region, whereby each charge-storage multi-layer is side-wall shaped, and the semiconductor substrate in some areas in the flat region are exposed; and

forming diffusion layers at the main surface of the semiconductor substrate by implanting impurities having a second conductivity type, which is different from the first conductivity type, from the exposed surface of the semiconductor substrate, and by diffusing the implanted impurities.

9. A method of manufacturing a nonvolatile semiconductor memory as claimed in claim 8, wherein the impurities to form the second well layer at the side surfaces of the step member are implanted from the directions, which are tilted from the axis perpendicular to the main surface of the semiconductor substrate.

10. A method of manufacturing a nonvolatile semiconductor memory as claimed in claim 8, further comprising:

forming a fourth silicon oxide layer on the main surface of the semiconductor substrate for covering the control electrode, and the charge-storage multi-layers;

forming a mask layer on the fourth silicon oxide in an area where the control electrode is formed, and forming contact holes in the fourth silicon oxide layer by removing the fourth silicon oxide layer in the flat region; and

forming conductive plugs by burying the contact holes with conductive martial.

11. A method of manufacturing a nonvolatile semiconductor memory as claimed in claim 10, wherein the fourth silicon oxide layer is removed by a highly selective etching process under which the etching speed of a silicon oxide layer is faster than that of a silicon nitride layer.