SHIELD PLATES FOR REDUCED FIELD COUPLING IN NONVOLATILE MEMORY
First Claim
1. A nonvolatile memory system, comprising:
- a plurality of adjacent charge storage regions formed along a substrate in a first direction, said charge storage regions having lower surface levels and upper surface levels;
a plurality of adjacent control gates formed above said plurality of charge storage regions in said first direction, said control gates having upper surface levels;
insulating members along sides of said charge storage regions facing adjacent charge storage regions in said first direction and along sides of said control gates facing adjacent control gates in said first direction, said insulating members extending from at least a level between said lower and upper surface levels of said charge storage regions to said upper surface levels of said control gate; and
conductive isolating members along sides of said insulating members facing said first direction, said isolating members insulated from said charge storage regions and said control gates by said insulating members.
3 Assignments
0 Petitions
Accused Products
Abstract
Shield plates for reduced coupling between charge storage regions in nonvolatile semiconductor memory devices, and associated techniques for forming the same, are provided. Electrical fields associated with charge stored in the floating gates or other charge storage regions of a memory device can couple to neighboring charge storage regions because of the close, and continually decreasing proximity of these regions. A shield plate can be formed adjacent to the bit line sides of floating gates that face opposing bit line sides of adjacent floating gates. Insulating layers can be formed between each shield plate and its corresponding adjacent charge storage region. The insulating layers can extend to the levels of the upper surfaces of the control gates formed above the charge storage regions. In such a configuration, sidewall fabrication techniques can be implemented to form the insulating members and shield plates. Each shield plate can be deposited and etched without complex masking to connect the control gates and shield plates. In one embodiment, the shield plates are at a floating potential.
-
Citations
39 Claims
-
1. A nonvolatile memory system, comprising:
-
a plurality of adjacent charge storage regions formed along a substrate in a first direction, said charge storage regions having lower surface levels and upper surface levels; a plurality of adjacent control gates formed above said plurality of charge storage regions in said first direction, said control gates having upper surface levels; insulating members along sides of said charge storage regions facing adjacent charge storage regions in said first direction and along sides of said control gates facing adjacent control gates in said first direction, said insulating members extending from at least a level between said lower and upper surface levels of said charge storage regions to said upper surface levels of said control gate; and conductive isolating members along sides of said insulating members facing said first direction, said isolating members insulated from said charge storage regions and said control gates by said insulating members. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
-
-
28. A nonvolatile memory system, comprising:
-
a plurality of adjacent charge storage regions having two substantially parallel sides in a bit line direction; a plurality of control gates formed above said adjacent charge storage regions having two substantially parallel sides in said bit line direction; an insulation member adjacent to each of said bit line sides of adjacent charge storage regions; and a floating conductive isolation member adjacent to each insulation member, each isolation member shielding a corresponding adjacent charge storage region. - View Dependent Claims (29, 30, 31, 32, 33)
-
-
34. A nonvolatile memory system, comprising:
-
charge storage regions having two substantially parallel bit line sides in a bit line direction; control gates above said charge storage regions, said control gates having two substantially parallel sides in said bit line direction; word lines extending in a word line direction substantially perpendicular to said bit line direction, each word line is associated with an individual one of said control gates; insulating members along bit line sides of said charge storage regions and control gates, each insulating member extending from a level above said substrate to above a lower level of it most adjacent control gate; a conductive isolation shield formed along each insulating member, each isolation shield insulated from an adjacent charge storage region and control gate by said each insulating member; and an electrical connection between each word line and one or more of said isolation shields adjacent to a charge storage region associated with said each word line. - View Dependent Claims (35, 36, 37, 38, 39)
-
Specification