SHIELD PLATES FOR REDUCED FIELD COUPLING IN NONVOLATILE MEMORY

• US 20080157169A1
• Filed: 12/28/2006
• Published: 07/03/2008
• Est. Priority Date: 12/28/2006
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Yuan, Jack H.
• Application Number:
  US11/617,598
• Publication Number:
  US 20080157169A1
• Time in Patent Office: Days
• US Class Current: 257/319
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Shield plates for reduced coupling between charge storage regions in nonvolatile semiconductor memory devices, and associated techniques for forming the same, are provided. Electrical fields associated with charge stored in the floating gates or other charge storage regions of a memory device can couple to neighboring charge storage regions because of the close, and continually decreasing proximity of these regions. A shield plate can be formed adjacent to the bit line sides of floating gates that face opposing bit line sides of adjacent floating gates. Insulating layers can be formed between each shield plate and its corresponding adjacent charge storage region. The insulating layers can extend to the levels of the upper surfaces of the control gates formed above the charge storage regions. In such a configuration, sidewall fabrication techniques can be implemented to form the insulating members and shield plates. Each shield plate can be deposited and etched without complex masking to connect the control gates and shield plates. In one embodiment, the shield plates are at a floating potential.

Claims

1. A nonvolatile memory system, comprising:

a plurality of adjacent charge storage regions formed along a substrate in a first direction, said charge storage regions having lower surface levels and upper surface levels;

a plurality of adjacent control gates formed above said plurality of charge storage regions in said first direction, said control gates having upper surface levels;

insulating members along sides of said charge storage regions facing adjacent charge storage regions in said first direction and along sides of said control gates facing adjacent control gates in said first direction, said insulating members extending from at least a level between said lower and upper surface levels of said charge storage regions to said upper surface levels of said control gate; and

conductive isolating members along sides of said insulating members facing said first direction, said isolating members insulated from said charge storage regions and said control gates by said insulating members.

2. The nonvolatile memory system of claim 1, wherein:

said conductive isolating members are floating.

3. The nonvolatile memory system of claim 1, further comprising:

rows of charge storage regions formed in a word line direction substantially perpendicular to said first direction, each charge storage region of said plurality of charge storage regions is part of an individual one of said rows, said first direction is a bit line direction; and

word lines extending in said word line direction, wherein each word line extends across a corresponding row of charge storage regions;

wherein each insulating member extends in said word line direction along one bit line side of each charge storage region in a respective row and one bit line side of said respective row'"'"'s corresponding word line;

wherein each conductive isolating member extends in said second direction along one of said insulating members;

wherein each isolating member includes an electrical connection to a word line formed above a row of charge storage regions to which said each isolating member is closest in said bit line direction.

4. The nonvolatile memory system of claim 3, wherein:

each word line is formed from a corresponding row of control gates in said second direction.

5. The nonvolatile memory system of claim 3, wherein:

each word line is formed above a corresponding row of control gates in said second direction and includes an electrical connection to its corresponding row of control gates.

6. The nonvolatile memory system of claim 3, wherein:

said electrical connection is provided at a portion of said word line that extends beyond a last charge storage region of said corresponding row of charge storage regions, said last charge storage region is a charge storage region farthest from row control circuitry for said word line.

7. The nonvolatile memory system of claim 3, wherein:

said electrical connection is provided at a portion of said word line between row control circuitry for said word line and a first charge storage region of said corresponding row of charge storage regions for said word line.

8. The nonvolatile memory system of claim 3, wherein:

said nonvolatile memory system includes a first plurality of bit lines having substantially equal spacing therebetween and a second plurality of bit lines having substantially equal spacing therebetween;

a last bit line of said first plurality of bit lines is adjacent to a first bit line of said second plurality of bit lines, said last bit line and said first bit line have a larger spacing therebetween than said substantially equal spacing between bit lines of said first plurality and bit lines of said second plurality; and

said electrical connection is provided at said larger spacing between said last bit line of said first plurality and said first bit line of said second plurality.

9. The nonvolatile memory system of claim 1, wherein:

said at least one conductive isolating member provides shielding from electrical field coupling based on charge stored in said adjacent charge storage regions.

10. The nonvolatile memory system of claim 9, wherein:

said isolating members shield said adjacent charge storage regions to reduce shifts in the apparent threshold voltages of storage elements formed from said charge storage regions and control gates.

11. The nonvolatile memory system of claim 1, wherein:

each conductive isolating member is capacitively coupled to its most adjacent charge storage region and control gate, thereby increasing a coupling ratio between said adjacent charge storage region and said adjacent control gate.

12. The nonvolatile memory system of claim 1, wherein:

said first direction corresponds to a bit line axis for a NAND string of flash memory devices formed from said plurality of charge storage regions and said plurality of control gates;

said insulating members comprise, for each pair of charge storage regions and control gates adjacent in said first direction, a first insulating member along a first bit line side of a first charge storage region of said pair and a first bit line side of a first control gate of said pair, and a second insulating member along a first bit line side of a second charge storage region of said pair and a first bit line side of a second control gate of said pair; and

said conductive isolating members comprise, for said each pair, a first isolating member along said first insulating member and a second isolating member along said second insulating member.

13. The nonvolatile memory system of claim 1, further comprising:

a first select gate adjacent to a first charge storage region of said plurality;

a second select gate adjacent to a last charge storage region of said plurality;

an insulating member formed along a bit line side of said first charge storage region adjacent to said first select gate;

an isolating member formed along said insulating member for said first charge storage region;

an insulating member formed along a bit line side of said last charge storage region adjacent to said second select gate; and

an isolating member formed along said insulating member for said last charge storage region.

14. The nonvolatile memory system of claim 1, wherein:

said first direction corresponds to a bit line axis for a NAND string of flash memory devices formed from said plurality of charge storage regions and said plurality of control gates;

said insulating members comprise, for each pair of charge storage regions and control gates adjacent in said first direction, a first insulating member along a first bit line side of a first charge storage region of said pair and a first bit line side of a first control gate of said pair, and a second insulating member along a first bit line side of a second charge storage region of said pair and a first bit line side of a second control gate of said pair; and

said conductive isolating members comprise, for said each pair, a single isolating member between said first insulating member and said second insulating member.

15. The nonvolatile memory system of claim 1, further comprising:

a plurality of word lines formed above said plurality of charge storage regions;

wherein each of said control gates forms part of an individual one of said word lines.

16. The nonvolatile memory system of claim 17, further comprising:

a plurality of word lines formed above said plurality of control gates;

wherein each control gate is electrically connected to an individual one of said word lines.

17. The nonvolatile memory system of claim 1, wherein:

each conductive isolating member is formed of polysilicon.

18. The nonvolatile memory system of claim 13, wherein:

each conductive isolating member is a conductive isolating sidewall deposited and etched to a thickness less than 50 angstroms.

19. The nonvolatile memory system of claim 1, wherein:

said insulating members are formed of at least one layer of oxide and/or nitride.

20. The nonvolatile memory system of claim 1, wherein:

each insulating member is an insulating sidewall deposited along a bit line side of a first charge storage region and a bit line side of a first control gate corresponding to said first charge storage region.

21. The nonvolatile memory system of claim 1, wherein:

said control gates consist of one or more layers of conductive material.

22. The nonvolatile memory system of claim 1, wherein:

said charge storage regions are conductive floating gate regions.

23. The nonvolatile memory system of claim 1, wherein:

said charge storage regions are dielectric charge storage regions.

24. The nonvolatile memory system of claim 1, wherein:

said charge storage regions are tailored dielectric layers.

25. The nonvolatile memory system of claim 1, further comprising:

a NAND string of nonvolatile storage elements, each nonvolatile storage element is comprised of one of said charge storage regions and one of said control gates.

26. The nonvolatile memory system of claim 25, further comprising:

an array of NAND flash memory devices including said NAND string.

27. The nonvolatile memory system of claim 1, wherein:

said plurality of charge storage regions and said plurality of control gates form multi-state flash memory devices.

28. A nonvolatile memory system, comprising:

a plurality of adjacent charge storage regions having two substantially parallel sides in a bit line direction;

a plurality of control gates formed above said adjacent charge storage regions having two substantially parallel sides in said bit line direction;

an insulation member adjacent to each of said bit line sides of adjacent charge storage regions; and

a floating conductive isolation member adjacent to each insulation member, each isolation member shielding a corresponding adjacent charge storage region.

29. The nonvolatile memory system of claim 28, wherein:

each charge storage region has two adjacent insulation members comprising first and second insulation sidewalls formed along respective ones of said two bit line sides.

30. The nonvolatile memory system of claim 29, wherein:

each of said first and second insulation sidewalls extends from a lower surface level of its adjacent charge storage region to an upper surface level of its adjacent control gate; and

each charge storage region has two adjacent isolation members including a first isolation sidewall formed along said first insulation member and a second isolation sidewall formed along said second insulation member, said first and second isolation sidewalls capacitively coupled to said each charge storage region and its corresponding control gate, thereby increasing a coupling ratio between said charge storage region and corresponding control gate.

31. The nonvolatile memory system of claim 29, further comprising:

rows of charge storage regions extending in a word line direction substantially perpendicular to said bit line direction, each charge storage region of said plurality of charge storage regions is part of an individual one of said rows;

a plurality of word lines extending across said rows of charge storage regions, said word lines including two bit line sides; and

wherein said first and second insulation members for a corresponding charge storage region are formed along respective bit line sides of each charge storage region in a corresponding row and said bit line sides of a word line for said corresponding row.

32. The nonvolatile memory system of claim 28, wherein:

said plurality of charge storage regions form a NAND string of nonvolatile storage elements; and

said NAND string is electrically connected with a plurality of additional NAND strings to form an array of flash storage devices.

33. The nonvolatile memory system of claim 28, wherein:

said plurality of charge storage regions form a plurality of multi-state flash memory devices.

34. A nonvolatile memory system, comprising:

charge storage regions having two substantially parallel bit line sides in a bit line direction;

control gates above said charge storage regions, said control gates having two substantially parallel sides in said bit line direction;

word lines extending in a word line direction substantially perpendicular to said bit line direction, each word line is associated with an individual one of said control gates;

insulating members along bit line sides of said charge storage regions and control gates, each insulating member extending from a level above said substrate to above a lower level of it most adjacent control gate;

a conductive isolation shield formed along each insulating member, each isolation shield insulated from an adjacent charge storage region and control gate by said each insulating member; and

an electrical connection between each word line and one or more of said isolation shields adjacent to a charge storage region associated with said each word line.

35. The nonvolatile memory system of claim 34, further comprising:

rows of charge storage regions extending in said word line direction, said insulating members extend in said word line direction along said bit line sides of each charge storage region in a corresponding row, said conductive isolation shields extend along said insulating members in said word line direction;

wherein said conductive isolation shields form first and second isolating sidewalls adjacent to each row of charge storage regions and on opposite sides thereof in said bit line direction; and

wherein said electrical connection for each word line includes an electrical connection to said first and second isolating sidewalls.

36. The nonvolatile memory system of claim 35, wherein:

said electrical connection for each word line is at a portion of said word line extending beyond a last charge storage region of said word line.

37. The nonvolatile memory system of claim 35, wherein:

said nonvolatile memory includes a first plurality of bit lines having substantially equally spacing therebetween and a second plurality of bit lines having substantially equal spacing therebetween;

a last bit line of said first plurality of bit lines is adjacent to a first bit line of said second plurality of bit lines, said last bit line and said first bit line have a larger spacing therebetween than said substantially equal spacing between bit lines of said first plurality and bit lines of said second plurality;

said electrical connection for each word line is provided at said larger spacing between said last bit of said first plurality and said first bit line of said second plurality.

38. The nonvolatile memory system of claim 35, wherein:

said electrical connection for each word line is at a portion of said word line before a first charge storage region of said word line and closest to row control circuitry associated with said word line.

39. The nonvolatile memory system of claim 34, wherein:

said charge storage regions form a plurality of multi-state NAND flash memory devices.