GEOMETRY OF MOS DEVICE WITH LOW ON-RESISTANCE

• US 20080157195A1
• Filed: 12/26/2007
• Published: 07/03/2008
• Est. Priority Date: 12/28/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited), Marvell Semiconductor, Inc. (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat, Krishnamoorthy, Ravishanker
• Granted Patent: US 9,466,596 B2
• Time in Patent Office: Days
• US Class Current: 257/337
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A Metal Oxide Semiconductor (MOS) device formed on a substrate and a method for forming the MOS device. The MOS device includes a drain region, a gate region surrounding the drain region, source regions arranged around the gate region and across from the drain region, and bulk regions arranged around the gate region and separating the source regions. The gate region is formed in a loop around the drain region. In this manner, the on-resistance (Ron) of a MOS device is decreased without also increasing the area of the MOS device.

Claims

1. A Metal Oxide Semiconductor (MOS) device formed on a substrate comprising:

a drain region;

a gate region surrounding the drain region and formed in a loop around the drain region;

a plurality of source regions arranged around the gate region and across from the drain region; and

a plurality of bulk regions arranged around the gate region and separating the source regions.

2. The MOS device of claim 1, wherein the gate region is formed in a closed loop.

3. The MOS device of claim 2, wherein gate region has a shape corresponding to that of the drain region.

4. The MOS device of claim 3, wherein the drain region has a multi-sided polygon shape including one of a square, a rectangle, a hexagon and an octagon.

5. The MOS device of claim 4, wherein the substrate has a shape corresponding to that of the drain region, and the bulk regions are arranged in corners of the substrate.

6. The MOS device of claim 3, wherein the drain region has a circular shape.

7. The MOS device of claim 1, wherein a channel region is formed beneath the gate region.

8. The MOS device of claim 7, wherein the channel region is configured so that current flows from each source region to the drain region.

9. The MOS device of claim 1, wherein the MOS device is a transistor.

10. The MOS device of claim 1, wherein the substrate is a silicon substrate, and the gate region includes polysilicon.

11. The MOS device of claim 10, wherein the MOS device is a Square DMOS (SQDMOS).

12. The MOS device of claim 1, wherein the drain region and at least one of the source regions have respective contacts, and the distance between the drain region contacts and the gate region is greater than the distance between the source region contacts and the gate region.

13. A Metal Oxide Semiconductor (MOS) device having a plurality of MOS transistor cells formed in an array on a substrate, each MOS transistor cell comprising:

a drain region;

a gate region surrounding the drain region and formed in a loop; and

a plurality of source regions arranged around the gate region and across from the drain region; and

a plurality of bulk regions arranged around the gate region and separating the source regions;

wherein the source regions overlap the corresponding source regions of an adjacent MOS transistor cell.

14. A method for forming a Metal Oxide Semiconductor (MOS) device on a substrate, comprising:

forming a drain region;

forming a gate region that surrounds the drain region in a loop;

forming a plurality of source regions arranged around the gate region and across from the drain region; and

forming a plurality of bulk regions arranged around the gate region and separating the source regions.

15. The method of claim 14, wherein the gate region is formed in a closed loop.

16. The method of claim 15, wherein gate region has a shape corresponding to that of the drain region.

17. The method of claim 16, wherein the drain region has a multi-sided polygon shape including one of a square, a rectangle, a hexagon and an octagon.

18. The method of claim 17, wherein the substrate has a shape corresponding to that of the drain region, and the bulk regions are arranged in corners of the substrate.

19. The method of claim 16, wherein the drain region has a circular shape.

20. The method of claim 14, further comprising forming a channel region beneath the gate region.

21. The method of claim 20, wherein the channel region is configured so that current flows from each source region to the drain region.

22. The method of claim 14 wherein the substrate is a silicon substrate, and the gate region includes polysilicon.

23. The method of claim 22, wherein the MOS device is a Square DMOS (SQDMOS).

24. The method of claim 14, further comprising forming respective contacts in the drain region and the source regions, wherein the distance between the drain region contacts and the gate region is greater than the distance between the source region contacts and the gate region.

25. A method for forming a Metal Oxide Semiconductor (MOS) transistor cell on a substrate comprising:

forming MOS transistor cells on the substrate, wherein each MOS transistor cell is formed by;

forming a drain region;

forming a gate region that surrounds the drain region in a loop;

forming a plurality of source regions arranged around the gate region and across from the drain region; and

forming a plurality of bulk regions arranged around the gate region and separating the source regions;

wherein the respective source regions of adjacent MOS transistor cells overlap.