Stressed barrier plug slot contact structure for transistor performance enhancement

• US 20080157208A1
• Filed: 12/29/2006
• Published: 07/03/2008
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chikarmane, Vinay B., Fischer, Kevin J., Peterson, Brennan L.
• Granted Patent: US 7,968,952 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.

Claims

1. A semiconductor structure comprising:

a transistor including a gate stack and a contact region, the gate stack defining a channel region thereunder; and

a slot contact in contact with a portion of the contact region;

wherein the slot contact induces a stress on the channel region.

2. The structure of claim 1, wherein the slot contact is further comprised of a barrier plug material.

3. The structure of claim 2, wherein the slot contact is further comprised of a contact metal and the volume of contact metal in the slot contact is greater than the volume of barrier plug in the slot contact.

4. The structure of claim 2, wherein the barrier plug material induces a stress on the channel region.

5. The structure of claim 3, wherein the barrier plug material is intrinsically stressed.

6. The structure of claim 5, wherein the slot contact is in contact with a portion of the contact region below the gate stack.

7. The structure of claim 5, wherein the barrier plug is intrinsically compressively stressed and induces a compressive stress on the channel region.

8. The structure of claim 5, wherein the barrier plug comprises Ta.

9. The structure of claim 8, wherein the barrier plug comprises a TaN and Ta bi-layer.

10. The structure of claim 5, wherein the barrier plug is intrinsically tensilely stressed.

11. The structure of claim 5, wherein at least 10% of the total slot contact height is located below the gate stack.

12. The structure of claim 5, wherein the contact metal comprises Cu.

13. A method of forming a semiconductor device comprising:

forming a transistor including a gate stack and a contact region, the gate stack defining a channel region thereunder;

disposing a dielectric layer over the transistor;

forming an opening in the dielectric layer to expose the contact region, the opening extending below the gate stack;

disposing a barrier plug within a portion of the opening, the barrier plug inducing a stress in the transistor channel region; and

filling the remaining of the opening with a contact metal.

14. The method of claim 13, further comprising recess etching a portion of source and drain regions prior to forming the contact region.

15. The method of claim 13, wherein recess etching comprises isotropic wet etching.

16. The method of claim 13, wherein the barrier plug is disposed with a bottom-up fill process.

17. A semiconductor structure comprising:

a first transistor including a first gate stack and a first contact region, the first gate stack defining a first channel region thereunder;

a second transistor including a second gate stack and a second contact region, the second gate stack defining a second channel region thereunder;

a dielectric layer disposed over the first and second transistors;

a contact opening formed in the dielectric layer, the opening exposing the first and second contact regions, the opening extending across an isolation region between the first transistor and second transistor;

a barrier plug material disposed within a portion of the contact opening, wherein the barrier plug material induces a stress in the first and second channel regions; and

a contact metal disposed on the barrier plug material.

18. The structure of claim 17, wherein the volume of contact metal within the contact opening is greater than the volume of the barrier plug within the opening.

19. The structure of claim 17, wherein the barrier plug is intrinsically stressed.

20. A semiconductor structure comprising:

a transistor including a gate stack and a contact region, the gate stack defining a channel region thereunder; and

a slot contact in contact with a portion of the contact region below the gate stack, the slot contact being at least twice as long as it is wide;

wherein the slot contact induces a stress on the channel region.

21. The structure of claim 20, wherein the slot contact includes an intrinsically stressed barrier plug and a contact metal.

22. The structure of claim 20, wherein the slot contact is approximately as long as the transistor width.

23. The structure of claim 20, wherein the slot contact is longer than the transistor width.